Post-Layout Optimization for Deep Submicron Design. - Koichi Sato; Masamichi Kawarabayashi; Hideyuki Emura; Naotaka Maeda (DAC, 1996)

Design methodology and tools for NEC electronics' structured ASIC ISSP. - Takumi Okamoto; Tsutomu Kimoto; Naotaka Maeda (ISPD, 2004)