Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks. - Romain Ritzenthaler; Tom Schram; Erik Bury; Jérôme Mitard; L.-Å. Ragnarsson; Guido Groeseneken; N. Horiguchi; Aaron Thean; Alessio Spessot; Christian Caillat; V. Srividya; Pierre Fazan (ESSDERC, 2012)

Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs. - Tommaso Romeo; Luigi Pantisano; Eddy Simoen; Raymond Krom; Mitsuhiro Togo; N. Horiguchi; Jérôme Mitard; Aaron Thean; Guido Groeseneken; Cor Claeys; Felice Crupi (ESSDERC, 2012)

Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications. - Jacopo Franco; Ben Kaczer; Jérôme Mitard; Maria Toledano-Luque; Felice Crupi; Geert Eneman; Ph. J. Rousse; Tibor Grasser; M. Cho; Thomas Kauerauf; Liesbeth Witters; Geert Hellings; et al. (ICICDT, 2012)

Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Mitsuhiro Togo; N. Horiguchi; Guido Groeseneken (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors. - Marc Aoulaiche; Eddy Simoen; Romain Ritzenthaler; Tom Schram; Hiroaki Arimura; Moonju Cho; Thomas Kauerauf; Guido Groeseneken; Naoto Horiguchi; Aaron Thean; Antonio Federico; Felice Crupi; et al. (ESSDERC, 2013)

Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

Holisitic device exploration for 7nm node. - Praveen Raghavan; Marie Garcia Bardon; Doyoung Jang; P. Schuddinck; Dmitry Yakimets; Julien Ryckaert; Abdelkarim Mercha; Naoto Horiguchi; Nadine Collaert; Anda Mocuta; Dan Mocuta; Zsolt Tokei; et al. (CICC, 2015)

Experimental evidences and simulations of trap generation along a percolation path. - Louis Gerrer; Razaidi Hussin; Salvatore M. Amoroso; Jacopo Franco; Pieter Weckx; Marko Simicic; N. Horiguchi; Ben Kaczer; Tibor Grasser; Asen Asenov (ESSDERC, 2015)

Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow. - Razaidi Hussin; Louis Gerrer; Jie Ding; Liping Wang; Salvatore M. Amoroso; Binjie Cheng; Dave Reid; Pieter Weckx; Marko Simicic; Jacopo Franco; Annelies Vanderheyden; Danielle Vanhaeren; et al. (ESSDERC, 2015)

Off-state stress degradation mechanism on advanced p-MOSFETs. - Moonju Cho; Alessio Spessot; Ben Kaczer; Marc Aoulaiche; Romain Ritzenthaler; Tom Schram; Pierre Fazan; Naoto Horiguchi; Dimitri Linten (ICICDT, 2015)

I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration. - Romain Ritzenthaler; Tom Schram; M. J. Cho; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Christian Caillat; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Assessment of SiGe quantum well transistors for DRAM peripheral applications. - Romain Ritzenthaler; Tom Schram; Geert Eneman; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs. - Alessio Spessot; Romain Ritzenthaler; Tom Schram; Marc Aoulaiche; Moonju Cho; Maria Toledano-Luque; Naoto Horiguchi; Pierre Fazan (ICICDT, 2015)

Impact of fin shape variability on device performance towards 10nm node. - Kazuyuki Tomida; Keizo Hiraga; Morin Dehan; Geert Hellings; Doyoung Jang; Kenichi Miyaguchi; Thomas Chiarella; Minsoo Kim; Anda Mocuta; Naoto Horiguchi; Abdelkarim Mercha; Diederik Verkest; et al. (ICICDT, 2015)

Time dependent variability in RMG-HKMG FinFETs: Impact of extraction scheme on stochastic NBTI. - Ankush Chaudhary; Ben Kaczer; Philippe J. Roussel; Thomas Chiarella; Naoto Horiguchi; Souvik Mahapatra (IRPS, 2015)

NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures. - Jacopo Franco; Ben Kaczer; Philippe J. Roussel; Erik Bury; Hans Mertens; Romain Ritzenthaler; Tibor Grasser; Naoto Horiguchi; Aaron Thean; Guido Groeseneken (IRPS, 2015)

Origins and implications of increased channel hot carrier variability in nFinFETs. - Ben Kaczer; Jacopo Franco; M. Cho; Tibor Grasser; Philippe J. Roussel; Stanislav Tyaginov; M. Bina; Yannick Wimmer; Luis-Miguel Procel; Lionel Trojman; Felice Crupi; Gregory Pitner; et al. (IRPS, 2015)

Towards high performance sub-10nm finW bulk FinFET technology. - Thomas Chiarella; Stefan Kubicek; E. Rosseel; Romain Ritzenthaler; Andriy Hikavyy; P. Eyben; An De Keersgieter; L.-Å. Ragnarsson; M.-S. Kim; S.-A. Chew; Tom Schram; S. Demuynck; et al. (ESSDERC, 2016)

PPAC scaling enablement for 5nm mobile SoC technology. - Mustafa Badaroglu; Jeff Xu; John Zhu; Da Yang 007; Jerry Bao; Seung Chul Song; Peijie Feng; Romain Ritzenthaler; Hans Mertens; Geert Eneman; Naoto Horiguchi; Jeffrey Smith 003; et al. (ESSDERC, 2017)

On the ballistic ratio in 14nm-Node FinFETs. - Fabian M. Bufler; Kenichi Miyaguchi; Thomas Chiarella; N. Horiguchi; Anda Mocuta (ESSDERC, 2017)

Isolation of nanowires made on bulk wafers by ground plane doping. - Romain Ritzenthaler; Hans Mertens; An De Keersgieter; Jérôme Mitard; Dan Mocuta; N. Horiguchi (ESSDERC, 2017)

ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology. - Marko Simicic; Geert Hellings; Shih-Hung Chen; Naoto Horiguchi; Dimitri Linten (ESSDERC, 2018)

New methodology for modelling MOL TDDB coping with variability. - Philippe J. Roussel; Adrian Vaisman Chasin; Steven Demuynck; Naoto Horiguchi; Dimitri Linten; Anda Mocuta (IRPS, 2018)

Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET. - Shimpei Yamaguchi; Liesbeth Witters; Jérôme Mitard; Geert Eneman; Geert Hellings; Andriy Hikavyy; Roger Loo; Naoto Horiguchi (Microelectron. Reliab., 2018)

Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors. - Eddy Simoen; Alberto Vinicius Oliveira; Anabela Veloso; Adrian Vaisman Chasin; Romain Ritzenthaler; Hans Mertens; Naoto Horiguchi; Cor Claeys (ASICON, 2019)

CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies. - Shih-Hung Chen; Dimitri Linten; Geert Hellings; Marko Simicic; Ben Kaczer; Thomas Chiarella; Hans Mertens; Jérôme Mitard; Anda Mocuta; N. Horiguchi (IRPS, 2019)

Study of the Mechanical Stress Impact on Silicide Contact Resistance by 4-Point Bending. - Yefan Liu; Hao Yu; Gaspard Hiblot; Anastasiia Kruv; Marc Schaekers; Naoto Horiguchi; Dimitrios Velenis; Ingrid De Wolf (IRPS, 2019)

Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices. - Barry J. O'Sullivan; Romain Ritzenthaler; Gerhard Rzepa; Z. Wu; E. Dentoni Litta; O. Richard; T. Conard; V. Machkaoutsan; Pierre Fazan; C. Kim; Jacopo Franco; Ben Kaczer; et al. (IRPS, 2019)

Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation. - Adrian Vaisman Chasin; Jacopo Franco; Erik Bury; Romain Ritzenthaler; Eugenio Dentoni Litta; Alessio Spessot; Naoto Horiguchi; Dimitri Linten; Ben Kaczer (IRPS, 2020)

Conduction and Breakdown Mechanisms in Low-k Spacer and Nitride Spacer Dielectric Stacks in Middle of Line Interconnects. - Chen Wu; Adrian Vaisman Chasin; Steven Demuynck; Naoto Horiguchi; Kris Croes (IRPS, 2020)

Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper. - Jacopo Franco; Hiroaki Arimura; J.-F. de Marneffe; A. Vandooren; L.-Å. Ragnarsson; Zhicheng Wu; Dieter Claes; E. Dentoni Litta; N. Horiguchi; Kris Croes; Dimitri Linten; Tibor Grasser; et al. (ICICDT, 2021)

Reliability of a DME Ru Semidamascene scheme with 16 nm wide Airgaps. - Alicja Lesniewska; Olalla Varela Pedreira; Melina Lofrano; Gayle Murdoch; Marleen H. van der Veen; Anish Dangol; Naoto Horiguchi; Zsolt Tökei; Kris Croes (IRPS, 2021)

Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling. - Anabela Veloso; Geert Eneman; An De Keersgieter; P. Favia; Andriy Hikavyy; Rongmei Chen; Anne Jourdain; N. Horiguchi (ICICDT, 2022)

Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations. - Alessio Spessot; Shairfe Muhammad Salahuddin; Ricardo Escobar; Romain Ritzenthaler; Yang Xiang; Rahul Budhwani; Eugenio Dentoni Litta; Elena Capogreco; Joao P. Bastos; Yangyin Chen; Naoto Horiguchi (IMW, 2022)

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery. - J. P. Bastos; Barry J. O'Sullivan; Jacopo Franco; Stanislav Tyaginov; Brecht Truijen; Adrian Vaisman Chasin; Robin Degraeve; Ben Kaczer; Romain Ritzenthaler; Elena Capogreco; E. Dentoni Litta; Alessio Spessot; et al. (IRPS, 2022)

Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets. - Erik Bury; Adrian Vaisman Chasin; Ben Kaczer; Michiel Vandemaele; Stanislav Tyaginov; Jacopo Franco; Romain Ritzenthaler; Hans Mertens; Pieter Weckx; N. Horiguchi; Dimitri Linten (IRPS, 2022)

High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories. - Romain Ritzenthaler; Elena Capogreco; E. Dupuy; Hiroaki Arimura; J. P. Bastos; P. Favia; F. Sebaai; D. Radisic; V. T. H. Nguyen; G. Mannaert; B. T. Chan; V. Machkaoutsan; et al. (VLSI Technology and Circuits, 2022)

Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. - Kateryna Serbulova; S.-H. Chen; Geert Hellings; Anabela Veloso; Anne Jourdain; Dimitri Linten; Jo De Boeck; Guido Groeseneken; Julien Ryckaert; Geert Van der Plas; Eric Beyne; Eugenio Dentoni Litta; et al. (VLSI Technology and Circuits, 2022)

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. - A. Vandooren; N. Parihar; Jacopo Franco; Roger Loo; Hiroaki Arimura; R. Rodriguez; F. Sebaai; S. Iacovo; Kevin Vandersmissen; W. Li; G. Mannaert; D. Radisic; et al. (VLSI Technology and Circuits, 2022)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

Reliability challenges in Forksheet Devices: (Invited Paper). - Erik Bury; Michiel Vandemaele; Jacopo Franco; Adrian Chasin; Stanislav Tyaginov; A. Vandooren; Romain Ritzenthaler; Hans Mertens; Javier Diaz-Fortuny; N. Horiguchi; Dimitri Linten; Ben Kaczer (IRPS, 2023)

Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET. - Hiroaki Arimura; S. Brus; Jacopo Franco; Yusuke Oniki; A. Vandooren; T. Conard; B. T. Chan; B. Kannan; M. Samiee; W. Li; P. Deminskyi; E. Shero; et al. (VLSI Technology and Circuits, 2023)

Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions. - Jacopo Franco; Hiroaki Arimura; J.-F. de Marneffe; S. Brus; Romain Ritzenthaler; E. Dentoni Litta; Kris Croes; Ben Kaczer; N. Horiguchi (VLSI Technology and Circuits, 2023)

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. - Hans Mertens; M. Hosseini; Thomas Chiarella; D. Zhou; S. Wang; G. Mannaert; E. Dupuy; D. Radisic; Z. Tao; Yusuke Oniki; Andriy Hikavyy; R. Rosseel; et al. (VLSI Technology and Circuits, 2023)

Integration of a Stacked Contact MOL for Monolithic CFET. - Victor Vega-Gonzalez; D. Radisic; Bt Chan; S. Choudhury; S. Wang; A. Mingardi; Q. Toan Le; H. Decoster; Yusuke Oniki; P. Puttarame; Kevin Vandersmissen; J. P. Soulie; et al. (VLSI Technology and Circuits, 2023)

Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics. - J. P. Bastos; Barry J. O'Sullivan; Yusuke Higashi; Adrian Vaisman Chasin; Jacopo Franco; Hiroaki Arimura; J. Ganguly; Elena Capogreco; Alessio Spessot; N. Horiguchi (IRPS, 2024)

SILC and TDDB reliability of novel low thermal budget RMG gate stacks. - Andrea Vici; Robin Degraeve; Naoto Horiguchi; Ingrid De Wolf; Jacopo Franco (IRPS, 2024)

Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs Using Rare-Earth Oxide-Based Dipole-First Gate Stack Compatible with CFET Integration. - Hiroaki Arimura; Hans Mertens; Jacopo Franco; L. Lukose; W. Maqsood; S. Brus; Thomas Chiarella; A. Impagnatiello; S. Homkar; V. K. Mootheri; C. Yin; G. Alessio Verni; et al. (VLSI Technology and Circuits, 2024)

Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts. - Steven Demuynck; Victor Vega-Gonzalez; C. Toledo de Carvalho Cavalcante; L. Petersen Barbosa Lima; K. Stiers; C. Sheng; A. Vandooren; M. Hosseini; X. Zhou; Hans Mertens; Thomas Chiarella; Jürgen Bömmels; et al. (VLSI Technology and Circuits, 2024)

DRAM-Peri FinFET - A Thermally-Stable High-Performance Advanced CMOS RMG Platform with Mo-Based pWFM for sub-10nm DRAM. - J. Ganguly; Hiroaki Arimura; Romain Ritzenthaler; H. Bana; J. W. Maes; J. G. Lai; S. Brus; W. Maqsood; R. Sarkar; B. Kannan; Elena Capogreco; V. Machkaoutsan; et al. (VLSI Technology and Circuits, 2024)

Transition-state-theory-based interpretation of Landau double well potential for ferroelectrics. - Md Nur K. Alam; Sergiu Clima; Ben Kaczer; Philippe Roussel; Brecht Truijen; Lars-Åke Ragnarsson; N. Horiguchi; Marc M. Heyns; Jan Van Houdt (CoRR, 2024)

Impact of Gate Metal Work Function on 1/f Noise in RMG MOSFETs. - R. Asanovski; Hiroaki Arimura; J. Ganguly; Pierpaolo Palestri; Alexander Grill; Ben Kaczer; Naoto Horiguchi; Luca Selmi; Jacopo Franco (IRPS, 2025)

Gate Stack Development for Next Gen High Voltage Periphery DRAM Devices. - J. P. Bastos; Jacopo Franco; Barry J. O'Sullivan; Yusuke Higashi; Adrian Chasin; J. Ganguly; Hiroaki Arimura; Alessio Spessot; M.-S. Kim; N. Horiguchi (IRPS, 2025)

TDDB Reliability Improvement of Low Thermal Budget RMG Stacks. - G. Molinaro; Hiroaki Arimura; S. Sacchi; Andrea Vici; Robin Degraeve; Ben Kaczer; Naoto Horiguchi; M. Houssa; Jacopo Franco (IRPS, 2025)