Performance Evaluation of Compiler Controlled Power Saving Scheme. - Jun Shirako; Munehiro Yoshida; Naoto Oshiyama; Yasutaka Wada; Hirofumi Nakano; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (ISHPC, 2005)

Compiler Control Power Saving Scheme for Multi Core Processors. - Jun Shirako; Naoto Oshiyama; Yasutaka Wada; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (LCPC, 2005)

A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput. - Kenta Yasufuku; Naoto Oshiyama; Toshitada Saito; Yukimasa Miyamoto; Yutaka Nakamura; Ryota Terauchi; Atsushi Kondo; Takuma Aoyama; Masafumi Takahashi; Yukihito Oowaki; Ryoichi Bandai (A-SSCC, 2014)