Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. - Naoya Onizawa; Akira Mochizuki; Takahiro Hanyu (ISMVL, 2005)

Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic. - Naoya Onizawa; Takahiro Hanyu (IEICE Trans. Electron., 2006)

High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. - Tasuku Nagai; Naoya Onizawa; Takahiro Hanyu (ISMVL, 2008)

Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling. - Kazuyasu Mizusawa; Naoya Onizawa; Takahiro Hanyu (IEICE Trans. Electron., 2008)

High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme. - Yo Ohtake; Naoya Onizawa; Takahiro Hanyu (ISCAS, 2009)

Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control. - Naoya Onizawa; Takahiro Hanyu (ISMVL, 2009)

High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving. - Naoya Onizawa; Takahiro Hanyu; Vincent C. Gaudet (IEICE Trans. Electron., 2009)

High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip. - Naoya Onizawa; Takahiro Hanyu (ISCAS, 2010)

One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control. - Atsushi Matsumoto; Naoya Onizawa; Takahiro Hanyu (ISMVL, 2010)

Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. - Naoya Onizawa; Tomoyoshi Funazaki; Atsushi Matsumoto; Takahiro Hanyu (ISVLSI (Selected papers), 2010)

Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link. - Naoya Onizawa; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2010)

Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning. - Naoya Onizawa; Takahiro Hanyu; Vincent C. Gaudet (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring. - Naoya Onizawa; Atsushi Matsumoto; Takahiro Hanyu (DATE, 2011)

Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system. - Takao Kawano; Naoya Onizawa; Atsushi Matsumoto; Takahiro Hanyu (ISCAS, 2011)

Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links. - Atsushi Matsumoto; Naoya Onizawa; Takahiro Hanyu (ISMVL, 2011)

Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding. - Naoya Onizawa; Vincent C. Gaudet; Takahiro Hanyu (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism. - Naoya Onizawa; Shoun Matsunaga; Vincent C. Gaudet; Takahiro Hanyu (ASYNC, 2012)

Architecture and implementation of an associative memory using sparse clustered networks. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Warren J. Gross (ISCAS, 2012)

Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links. - Atsushi Matsumoto; Naoya Onizawa; Takahiro Hanyu (ISMVL, 2012)

Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes. - Naoya Onizawa; Vincent C. Gaudet; Takahiro Hanyu; Warren J. Gross (ISMVL, 2012)

Multi-chip NoCs for Automotive Applications. - Tomohiro Yoneda; Masashi Imai; Naoya Onizawa; Atsushi Matsumoto; Takahiro Hanyu (PRDC, 2012)

Clockless Stochastic Decoding of Low-Density Parity-Check Codes. - Naoya Onizawa; Warren J. Gross; Takahiro Hanyu; Vincent C. Gaudet (SiPS, 2012)

Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling. - Naoya Onizawa; Atsushi Matsumoto; Takahiro Hanyu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A low-power Content-Addressable Memory based on clustered-sparse networks. - Hooman Jarollahi; Vincent Gripon; Naoya Onizawa; Warren J. Gross (ASAP, 2013)

A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems. - Naoya Onizawa; Warren J. Gross; Takahiro Hanyu (ASYNC, 2013)

Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks. - Naoya Onizawa; Warren J. Gross (DAC, 2013)

Selective decoding in associative memories based on Sparse-Clustered Networks. - Hooman Jarollahi; Naoya Onizawa; Warren J. Gross (GlobalSIP, 2013)

Reduced-complexity binary-weight-coded associative memories. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Warren J. Gross (ICASSP, 2013)

Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating. - Naoya Onizawa; Warren J. Gross; Takahiro Hanyu; Vincent C. Gaudet (ISMVL, 2013)

High-throughput CAM based on a synchronous overlapped search scheme. - Naoya Onizawa; Shoun Matsunaga; Vincent C. Gaudet; Warren J. Gross; Takahiro Hanyu (IEICE Electron. Express, 2013)

Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links. - Naoya Onizawa; Atsushi Matsumoto; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2013)

Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link. - Akira Mochizuki; Hirokatsu Shirahama; Naoya Onizawa; Takahiro Hanyu (APCCAS, 2014)

A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure. - Naoya Onizawa; Shoun Matsunaga; Takahiro Hanyu (ASYNC, 2014)

Associative Memories Based on Multiple-Valued Sparse Clustered Networks. - Hooman Jarollahi; Naoya Onizawa; Takahiro Hanyu; Warren J. Gross (ISMVL, 2014)

Soft-Delay-Error Evaluation in Content-Addressable Memory. - Naoya Onizawa; Shoun Matsunaga; Noboru Sakimura; Ryusuke Nebashi; Tadahiko Sugibayashi; Takahiro Hanyu (ISMVL, 2014)

Analog-to-stochastic converter using magnetic-tunnel junction devices. - Naoya Onizawa; Daisaku Katagiri; Warren J. Gross; Takahiro Hanyu (NANOARCH, 2014)

Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM. - Naoya Onizawa; Shoun Matsunaga; Takahiro Hanyu (NEWCAS, 2014)

Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Takahiro Hanyu; Warren J. Gross (SiPS, 2014)

A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Noboru Sakimura; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu; Warren J. Gross (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element. - Naoya Onizawa; Takahiro Hanyu (IEICE Electron. Express, 2014)

Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model. - Naoya Onizawa; Warren J. Gross; Takahiro Hanyu; Vincent C. Gaudet (IEICE Trans. Inf. Syst., 2014)

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. - Naoya Onizawa; Akira Mochizuki; Hirokatsu Shirahama; Masashi Imai; Tomohiro Yoneda; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2014)

High-Throughput Compact Delay-Insensitive Asynchronous NoC Router. - Naoya Onizawa; Atsushi Matsumoto; Tomoyoshi Funazaki; Takahiro Hanyu (IEEE Trans. Computers, 2014)

High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism. - Naoya Onizawa; Shoun Matsunaga; Vincent C. Gaudet; Warren J. Gross; Takahiro Hanyu (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Warren J. Gross (J. Signal Process. Syst., 2014)

Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model. - Naoya Onizawa; Warren J. Gross; Takahiro Hanyu; Vincent C. Gaudet (J. Signal Process. Syst., 2014)

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. - Takahiro Hanyu; Daisuke Suzuki; Naoya Onizawa; Shoun Matsunaga; Masanori Natsui; Akira Mochizuki (DATE, 2015)

Frequency-flexible stochastic Gabor filter. - Naoya Onizawa; Daisaku Katagiri; Kazumichi Matsumiya; Warren J. Gross; Takahiro Hanyu (DSP, 2015)

Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors. - Daisaku Katagiri; Naoya Onizawa; Takahiro Hanyu (ISMVL, 2015)

Scaled IIR filter based on stochastic computation. - Naoya Onizawa; Shunsuke Koshita; Takahiro Hanyu (MWSCAS, 2015)

A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery. - Naoya Onizawa; Akira Mochizuki; Akira Tamakoshi; Takahiro Hanyu (NANOARCH, 2015)

Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop. - Satoshi Oosawa; Takayuki Konishi; Naoya Onizawa; Takahiro Hanyu (NEWCAS, 2015)

Stochastic implementation of the disparity energy model for depth perception. - Kaushik Boga; Naoya Onizawa; François Leduc-Primeau; Kazumichi Matsumiya; Takahiro Hanyu; Warren J. Gross (SiPS, 2015)

Gabor Filter Based on Stochastic Computation. - Naoya Onizawa; Daisaku Katagiri; Kazumichi Matsumiya; Warren J. Gross; Takahiro Hanyu (IEEE Signal Process. Lett., 2015)

Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks. - Hooman Jarollahi; Vincent Gripon; Naoya Onizawa; Warren J. Gross (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Gammatone filter based on stochastic computation. - Naoya Onizawa; Shunsuke Koshita; Shuichi Sakamoto; Masahide Abe; Masayuki Kawamata; Takahiro Hanyu (ICASSP, 2016)

Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation. - Shunsuke Koshita; Naoya Onizawa; Masahide Abe; Takahiro Hanyu; Masayuki Kawamata (ISMVL, 2016)

VLSI implementation of deep neural networks using integral stochastic computing. - Arash Ardakani; François Leduc-Primeau; Naoya Onizawa; Takahiro Hanyu; Warren J. Gross (ISTC, 2016)

Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations. - Naoya Onizawa; Takahiro Hanyu (NEWCAS, 2016)

Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. - Naoya Onizawa; Hooman Jarollahi; Takahiro Hanyu; Warren J. Gross (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. - Naoya Onizawa; Noboru Sakimura; Ryusuke Nebashi; Tadahiko Sugibayashi; Takahiro Hanyu (J. Multiple Valued Log. Soft Comput., 2016)

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. - Takahiro Hanyu; Tetsuo Endoh; Daisuke Suzuki; Hiroki Koike; Yitao Ma; Naoya Onizawa; Masanori Natsui; Shoji Ikeda; Hideo Ohno (Proc. IEEE, 2016)

Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. - Takahiro Hanyu; Daisuke Suzuki; Naoya Onizawa; Masanori Natsui (DATE, 2017)

Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability. - Naoya Onizawa; Kazumichi Matsumiya; Warren J. Gross; Takahiro Hanyu (ESSCIRC, 2017)

Design of stochastic asymmetric compensation filters for auditory signal processing. - Naoya Onizawa; Shunsuke Koshita; Shuichi Sakamoto; Masayuki Kawamata; Takahiro Hanyu (GlobalSIP, 2017)

Evaluation of Stochastic Cascaded IIR Filters. - Naoya Onizawa; Shunsuke Koshita; Shuichi Sakamoto; Masayuki Kawamata; Takahiro Hanyu (ISMVL, 2017)

NoC-MRAM architecture for memory-based computing: Database-search case study. - Mostafa Rizk; Jean-Philippe Diguet; Naoya Onizawa; Amer Baghdadi; Martha Johanna Sepúlveda; Y. Akgul; Vincent Gripon; Takahiro Hanyu (NEWCAS, 2017)

High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation. - Shunsuke Koshita; Naoya Onizawa; Masahide Abe; Takahiro Hanyu; Masayuki Kawamata (IEICE Trans. Inf. Syst., 2017)

Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors. - Naoya Onizawa; Akira Mochizuki; Akira Tamakoshi; Takahiro Hanyu (IEEE Trans. Emerg. Top. Comput., 2017)

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. - Arash Ardakani; François Leduc-Primeau; Naoya Onizawa; Takahiro Hanyu; Warren J. Gross (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation. - Naoya Onizawa; Shunsuke Koshita; Shuichi Sakamoto; Masahide Abe; Masayuki Kawamata; Takahiro Hanyu (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Study of Stochastic Invertible Multiplier Designs. - Kaito Nishino; Sean C. Smithson; Naoya Onizawa; Brett H. Meyer; Warren J. Gross; Hitoshi Yamagata; Hiroyuki Fujita; Takahiro Hanyu (ICECS, 2018)

High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure. - Shunsuke Koshita; Naoya Onizawa; Masahide Abe; Takahiro Hanyu; Masayuki Kawamata (ISCAS, 2018)

Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter. - Shogo Mukaida; Naoya Onizawa; Takahiro Hanyu (ISMVL, 2018)

An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling. - Naoya Onizawa; Daisaku Katagiri; Kazumichi Matsumiya; Warren J. Gross; Takahiro Hanyu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

MTJ-based asynchronous circuits for Re-initialization free computing against power failures. - Naoya Onizawa; Masashi Imai; Tomohiro Yoneda; Takahiro Hanyu (Microelectron. J., 2018)

Networked Power-Gated MRAMs for Memory-Based Computing. - Jean-Philippe Diguet; Naoya Onizawa; Mostafa Rizk; Martha Johanna Sepúlveda; Amer Baghdadi; Takahiro Hanyu (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception. - Kaushik Boga; François Leduc-Primeau; Naoya Onizawa; Kazumichi Matsumiya; Takahiro Hanyu; Warren J. Gross (J. Signal Process. Syst., 2018)

Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN. - Ren Arakawa; Naoya Onizawa; Jean-Philippe Diguet; Takahiro Hanyu (ICECS, 2019)

Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge. - Naoya Onizawa; Warren J. Gross; Takahiro Hanyu (ICECS, 2019)

FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic. - Duckgyu Shin; Naoya Onizawa; Takahiro Hanyu (ICECS, 2019)

Efficient CMOS Invertible Logic Using Stochastic Computing. - Sean C. Smithson; Naoya Onizawa; Brett H. Meyer; Warren J. Gross; Takahiro Hanyu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices. - Akira Tamakoshi; Naoya Onizawa; Hitoshi Yamagata; Hiroyuki Fujita; Takahiro Hanyu (NEWCAS, 2020)

Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic. - Duckgyu Shin; Naoya Onizawa; Warren J. Gross; Takahiro Hanyu (IEEE Access, 2020)

Design Automation of Invertible Logic Circuit from a Standard HDL Description. - Makoto Kato; Naoya Onizawa; Takahiro Hanyu (FLAP, 2020)

Design of an MTJ-based Nonvolatile Multi-context Ternary Content-addressable Memory. - Naoya Onizawa; Ren Arakawa; Takahiro Hanyu (FLAP, 2020)

Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic. - Naoya Onizawa; Duckgyu Shin; Takahiro Hanyu (FLAP, 2020)

In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning. - Naoya Onizawa; Sean C. Smithson; Brett H. Meyer; Warren J. Gross; Takahiro Hanyu (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Memristive Computational Memory Using Memristor Overwrite Logic (MOL). - Khaled Alhaj Ali; Mostafa Rizk; Amer Baghdadi; Jean-Philippe Diguet; Jalal Jomaah; Naoya Onizawa; Takahiro Hanyu (IEEE Trans. Very Large Scale Integr. Syst., 2020)

High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter. - Naoya Onizawa; Shogo Mukaida; Akira Tamakoshi; Hitoshi Yamagata; Hiroyuki Fujita; Takahiro Hanyu (IEEE Trans. Very Large Scale Integr. Syst., 2020)

High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians. - Naoya Onizawa; Takahiro Hanyu (ISCAS, 2021)

Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices. - Naoya Onizawa; Akira Tamakoshi; Takahiro Hanyu (SiPS, 2021)

Sparse Random Signals for Fast Convergence on Invertible Logic. - Naoya Onizawa; Makoto Kato; Hitoshi Yamagata; Koji Yano; Seiichi Shin; Hiroyuki Fujita; Takahiro Hanyu (IEEE Access, 2021)

Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices. - Naoya Onizawa; Akira Tamakoshi; Takahiro Hanyu (IEEE Open J. Circuits Syst., 2021)

A Design Framework for Invertible Logic. - Naoya Onizawa; Kaito Nishino; Sean C. Smithson; Brett H. Meyer; Warren J. Gross; Hitoshi Yamagata; Hiroyuki Fujita; Takahiro Hanyu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN. - Ren Arakawa; Naoya Onizawa; Jean-Philippe Diguet; Takahiro Hanyu (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing. - Kota Katsuki; Duckgyu Shin; Naoya Onizawa; Takahiro Hanyu (ICECS 2022, 2022)

Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN. - Duckgyu Shin; Naoya Onizawa; Takahiro Hanyu (FLAP, 2022)

Stochastic Implementation of Simulated Quantum Annealing on PYNQ. - Taiga Kubuta; Duckgyu Shin; Naoya Onizawa; Takahiro Hanyu (ICFPT, 2023)

Improving Stochastic Quantum-Like Annealing Based on Rerandomization. - Ryoma Sasaki; Duckgyu Shin; Naoya Onizawa; Takahiro Hanyu (ICECS, 2023)

Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic. - Naoya Onizawa; Koji Yano; Seiichi Shin; Hiroyuki Fujita; Takahiro Hanyu (IEEE Access, 2023)

Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems. - Naoya Onizawa; Ryoma Sasaki; Duckgyu Shin; Warren J. Gross; Takahiro Hanyu (CoRR, 2023)

Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing. - Naoya Onizawa; Kyo Kuroki; Duckgyu Shin; Takahiro Hanyu (CoRR, 2023)

Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. - Duckgyu Shin; Naoya Onizawa; Warren J. Gross; Takahiro Hanyu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing. - Naoya Onizawa; Kota Katsuki; Duckgyu Shin; Warren J. Gross; Takahiro Hanyu (IEEE Trans. Neural Networks Learn. Syst., 2023)

Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning. - R. Kanda; Naoya Onizawa; Mathieu Léonardon; Vincent Gripon; Takahiro Hanyu (MWSCAS, 2024)

Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems. - Naoya Onizawa; Ryoma Sasaki; Duckgyu Shin; Warren J. Gross; Takahiro Hanyu (IEEE Access, 2024)

Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware. - R. Kanda; Hugo Le Blevec; Naoya Onizawa; Mathieu Léonardon; Vincent Gripon; Takahiro Hanyu (ISCAS, 2025)

Generating Hamiltonians with Known Minimum Energy Based on Ground-State Spin Logic for Probabilistic-Bit-Based Simulated Annealing. - Naoya Onizawa; Takahiro Hanyu (ISMVL, 2025)