Fast Implementation of Public-Key Cryptography ona DSP TMS320C6201. - Kouichi Itoh; Masahiko Takenaka; Naoya Torii; Syouji Temma; Yasushi Kurihara (CHES, 1999)

Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA. - Souichi Okada; Naoya Torii; Kouichi Itoh; Masahiko Takenaka (CHES, 2000)

The Block Cipher SC2000. - Takeshi Shimoyama; Hitoshi Yanami; Kazuhiro Yokoyama; Masahiko Takenaka; Kouichi Itoh; Jun Yajima; Naoya Torii; Hidema Tanaka (FSE, 2001)

DPA Countermeasure Based on the "Masking Method". - Kouichi Itoh; Masahiko Takenaka; Naoya Torii (ICISC, 2001)

DPA Countermeasures by Improving the Window Method. - Kouichi Itoh; Jun Yajima; Masahiko Takenaka; Naoya Torii (CHES, 2002)

Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm. - Shoichi Masui; Kenji Mukaida; Masahiko Takenaka; Naoya Torii (IEICE Trans. Electron., 2005)

Foreword. - Naoya Torii (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches. - Hirotaka Kokubo; Dai Yamamoto; Masahiko Takenaka; Kouichi Itoh; Naoya Torii (CARDIS, 2013)

A Spoofing Attack against a Cancelable Biometric Authentication Scheme. - Tetsuya Izu; Yumi Sakemi; Masahiko Takenaka; Naoya Torii (AINA, 2014)

Security Evaluation of Bistable Ring PUFs on FPGAs using Differential and Linear Analysis. - Dai Yamamoto; Masahiko Takenaka; Kazuo Sakiyama; Naoya Torii (FedCSIS, 2014)

A Technique Using PUFs for Protecting Circuit Layout Designs against Reverse Engineering. - Dai Yamamoto; Masahiko Takenaka; Kazuo Sakiyama; Naoya Torii (IWSEC, 2014)

Dynamic Behavior of RS latches using FIB processing and probe connection. - Naoya Torii; Dai Yamamoto; Masahiko Takenaka; Tsutomu Matsumoto (IACR Cryptol. ePrint Arch., 2014)

A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs. - Dai Yamamoto; Kazuo Sakiyama; Mitsugu Iwamoto; Kazuo Ohta; Masahiko Takenaka; Kouichi Itoh; Naoya Torii (J. Cryptogr. Eng., 2015)

Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs. - Naoya Torii; Dai Yamamoto; Tsutomu Matsumoto (TrustED@CCS, 2016)

Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs. - Naoya Torii; Dai Yamamoto; Tsutomu Matsumoto (CANDAR, 2016)

ASIC implementation of random number generators using SR latches and its evaluation. - Naoya Torii; Hirotaka Kokubo; Dai Yamamoto; Kouichi Itoh; Masahiko Takenaka; Tsutomu Matsumoto (EURASIP J. Inf. Secur., 2016)

Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks. - Naoya Torii; Dai Yamamoto; Masahiko Takenaka; Tsutomu Matsumoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Side-channel attack on COSO-based TRNG to estimate output bits. - Kotaro Hayashi; Ryuichi Minagawa; Naoya Torii (CANDARW, 2022)

Implementation and Evaluation of Ring Oscillator-based True Random Number Generator. - Naoya Torii; Ryuichi Minagawa; Hideaki Kevin Omae; Kotaro Hayashi (Int. J. Netw. Comput., 2022)