Network Testing for Digital Data Networks. - Naoya Watanabe; Ken-ichi Yukimatsu; Toshiaki Doi; Masachika Ishizura; Etsugo Yoneda; Makoto Kawashima; Kazuhiro Hayashi (ICC, 1986)

Multicast Communication Facilities in a High Speed Packet Switching Network. - Ken-ichi Yukimatsu; Naoya Watanabe; Takashi Honda (ICCC, 1986)

Evaluation of error recovery schemes for a high-speed packet switched network: link-by-link versus edge-to-edge schemes. - Tatsuya Suda; Naoya Watanabe (INFOCOM, 1988)

Evaluation of the Effects of Protocol Processing Overhead in Error Recovery Schemes for a High-Speed Packet Switched Network: Link-by-Link versus Edge-to-Edge Schemes. - Jaime Jungok Bae; Tatsuya Suda; Naoya Watanabe (IEEE J. Sel. Areas Commun., 1991)

A 90-MHz 16-Mb system integrated memory with direct interface to CPU. - Katsumi Dosaka; Akira Yamazaki; Naoya Watanabe; Hideaki Abe; Jun Ohtani; Toshiyuki Ogawa; Kazunori Ishihara; Masaki Kumanoya (IEEE J. Solid State Circuits, 1996)

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. - Yasunobu Nakase; Yoshikazu Morooka; David J. Perlman; Daniel J. Kolor; Jae-Myoung Choi; Hyun J. Shin; Tsutomu Yoshimura; Naoya Watanabe; Yoshio Matsuda; Masaki Kumanoya; Michihiro Yamada (IEEE J. Solid State Circuits, 1999)

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. - Akira Yamazaki; Fukashi Morishita; Naoya Watanabe; Teruhiko Amano; Masaru Haraguchi; Hideyuki Noda; Atsushi Hachisuka; Katsumi Dosaka; Kazutami Arimoto; Setsuo Wake; Hideyuki Ozaki; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

High frequency signal transmission characteristics of cone bump interconnections. - Akihiro Ikeda; Naoya Watanabe; Tanemasa Asano (3DIC, 2011)

PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. - Katsuya Kikuchi; Chihiro Ueda; Fumiaki Fujii; Yutaka Akiyama; Naoya Watanabe; Yasuhiro Kitamura; Toshio Gomyo; Toshikazu Okubo; Tetsuya Koyama; Tadashi Kamada; Masahiro Aoyagi; Kanji Otsuka (3DIC, 2011)

Low-temperature bonding of LSI chips to PEN film using Au cone bump for heterogeneous integration. - Takanori Shuto; Naoya Watanabe; Akihiro Ikeda; Tanemasa Asano (3DIC, 2011)

Damage evaluation of wet-chemical silicon-wafer thinning process. - Naoya Watanabe; Takumi Miyazaki; Masahiro Aoyagi; Kazuhiro Yoshikawa (3DIC, 2011)

New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. - Masahiro Aoyagi; Naoya Watanabe; Motohiro Suzuki; Katsuya Kikuchi; Shunsuke Nemoto; Noriaki Arima; Misaki Ishizuka; Koji Suzuki; Toshio Shiomi (3DIC, 2013)

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. - Isamu Hayashi; Teruhiko Amano; Naoya Watanabe; Yuji Yano; Yasuto Kuroda; M. Shirata; Katsumi Dosaka; Koji Nii; Hideyuki Noda; Hiroyuki Kawai (IEEE J. Solid State Circuits, 2013)

Analysis of thermal stress distribution for TSV with novel structure. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (3DIC, 2014)

Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. - Bui Thanh Tung 001; Xiaojin Cheng; Naoya Watanabe; Fumiki Kato; Katsuya Kikuchi; Masahiro Aoyagi (3DIC, 2014)

Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal. - Naoya Watanabe; Masahiro Aoyagi; Daisuke Katagawa; Tsubasa Bandoh; Takahiko Mitsui; Eiichi Yamamoto (3DIC, 2014)

13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM. - Koji Nii; Teruhiko Amano; Naoya Watanabe; Minoru Yamawaki; Kenji Yoshinaga; Mihoko Wada; Isamu Hayashi (ISSCC, 2014)

Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner. - Tung Thanh Bui 001; Naoya Watanabe; Masahiro Aoyagi; Katsuya Kikuchi (3DIC, 2015)

Wet cleaning process for high-yield via-last TSV formation. - Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi; Hidekazu Kikuchi; Azusa Yanagisawa; Akio Nakamura (3DIC, 2016)

Fabrication and stress analysis of annular-trench-isolated TSV. - Wei Feng; Tung Thanh Bui 001; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (Microelectron. Reliab., 2016)

Validation of TSV thermo-mechanical simulation by stress measurement. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (Microelectron. Reliab., 2016)

Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. - Samson Melamed; Naoya Watanabe; Shunsuke Nemoto; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (Microelectron. Reliab., 2016)

Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. - Samson Melamed; Naoya Watanabe; Shunsuke Nemoto; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (Microelectron. Reliab., 2017)

Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (3DIC, 2019)

Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. - Takuji Miki; Makoto Nagata; Akihiro Tsukioka; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (3DIC, 2019)

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. - Takuji Miki; Makoto Nagata; Hiroki Sonoda; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEEE J. Solid State Circuits, 2020)

Landside capacitor efficacy among multi-chip-module using Si-interposer. - Yuuki Araga; Ryo Kasai; Daisuke Tanaka; Yoshihide Murakami; Kyoshi Mihara; Kazuo Makida; Hiroki Sonoda; Makoto Nagata; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEICE Electron. Express, 2021)

Analysis and evaluation of noise coupling between through-silicon-vias. - Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEICE Electron. Express, 2021)