A video codec LSI for high-definition TV systems with one-transistor DRAM line memories. - Tomoji Takada; Takeshi Oto; Kazukuni Kitagaki; Naoyuki Hatanaka; Tatsuhiko Demura; Hiromichi Fuji; Toshinori Odaka; Hiroshi Sue; Tadahiro Oku (IEEE J. Solid State Circuits, 1989)

A floating-point cell library and a 100-Mflops image signal processor. - Hiroshige Fujii; Chikahiro Hori; Tomoji Takada; Naoyuki Hatanaka; Tatsuhiko Demura; Goichi Ootomo (IEEE J. Solid State Circuits, 1992)

A low-power design method using multiple supply voltages. - Mutsunori Igarashi; Kimiyoshi Usami; Kazutaka Nogami; Fumihiro Minami; Yukio Kawasaki; Takahiro Aoki; Midori Takano; Chiharo Mizuno; Takashi Ishikawa; Masahiro Kanazawa; Shinji Sonoda; Makoto Ichida; et al. (ISLPED, 1997)