Low-power technique for on-chip memory using biased partitioning and access concentration. - Naoyuki Kawabe; Kimiyoshi Usami (CICC, 2000)

Function-level power estimation methodology for microprocessors. - Gang Qu 001; Naoyuki Kawabe; Kimiyoshi Usami; Miodrag Potkonjak (DAC, 2000)

Automated selective multi-threshold design for ultra-low standby applications. - Kimiyoshi Usami; Naoyuki Kawabe; Masayuki Koizumi; Katsuhiro Seta; Toshiyuki Furusawa (ISLPED, 2002)

Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications. - Kimiyoshi Usami; Naoyuki Kawabe; Masayuki Koizumi; Katsuhiro Seta; Toshiyuki Furusawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Code Coverage-Based Power Estimation Techniques for Microprocessors. - Gang Qu 001; Naoyuki Kawabe; Kimiyoshi Usami; Miodrag Potkonjak (J. Circuits Syst. Comput., 2002)

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. - Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Chen Kong Teh; Takayoshi Shimazawa; Naoyuki Kawabe; Takeshi Kitahara; Yu Kikuchi; Tsuyoshi Nishikawa; Makoto Takahashi; Yukihito Oowaki (CICC, 2005)

Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. - Takeshi Kitahara; Naoyuki Kawabe; Fumihiro Minami; Katsuhiro Seta; Toshiyuki Furusawa (DATE, 2005)

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. - Toshihide Fujiyoshi; Shinichiro Shiratake; Shuou Nomura; Tsuyoshi Nishikawa; Yoshiyuki Kitasho; Hideho Arakida; Yuji Okuda; Yoshiro Tsuboi; Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Fumitoshi Hatori; et al. (IEEE J. Solid State Circuits, 2006)

An automated runtime power-gating scheme. - Mototsugu Hamada; Takeshi Kitahara; Naoyuki Kawabe; Hironori Sato; Tsuyoshi Nishikawa; Takayoshi Shimazawa; Takahiro Yamashita; Hiroyuki Hara; Yukihito Oowaki (ICCD, 2007)

A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique. - Kentaro Yoshioka; Hiroshi Kubota; Tomonori Fukushima; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Kaori Watanabe; Yoshinari Ojima; Katsuyuki Kimura; Sohichiroh Hosoda; Yutaka Ota; Tomohiro Koizumi; et al. (ISSCC, 2018)

A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC. - Kentaro Yoshioka; Hiroshi Kubota; Tomonori Fukushima; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Kaori Watanabe; Masatoshi Hirono; Yoshinari Ojima; Katsuyuki Kimura; Sohichiroh Hosoda; Yutaka Ota; et al. (IEEE J. Solid State Circuits, 2018)