Optimal Parallel Hardware K-Sorter and Top K-Sorter, with FPGA Implementations. - Naoyuki Matsumoto; Koji Nakano; Yasuaki Ito (ISPDC, 2015)

A Hardware Sorter for Almost Sorted Sequences, with FPGA Implementations. - Naoaki Harada; Naoyuki Matsumoto; Koji Nakano; Yasuaki Ito (CANDAR, 2016)