High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. - Naran Sirisantana; Liqiong Wei; Kaushik Roy 001 (ICCD, 2000)

Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. - Naran Sirisantana; Aiqun Cao; Shawn Davidson; Cheng-Kok Koh; Kaushik Roy 001 (ISLPED, 2001)

Synthesis of Selectively Clocked Skewed Logic Circuits. - Aiqun Cao; Naran Sirisantana; Cheng-Kok Koh; Kaushik Roy 001 (ISQED, 2002)

Skewed CMOS: noise-tolerant high-performance low-power static circuit family. - Alexandre Solomatnikov; Dinesh Somasekhar; Naran Sirisantana; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Integer linear programming-based synthesis of skewed logic circuits. - Aiqun Cao; Naran Sirisantana; Cheng-Kok Koh; Kaushik Roy 001 (ASP-DAC, 2003)

Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. - Naran Sirisantana; Kaushik Roy 001 (DATE, 2003)

A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies. - Naran Sirisantana; Kaushik Roy 001 (ESSCIRC, 2003)

Enhancing Yield at the End of the Technology Roadmap. - Naran Sirisantana; Bipul Chandra Paul; Kaushik Roy 001 (IEEE Des. Test Comput., 2004)

Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses. - Naran Sirisantana; Kaushik Roy 001 (IEEE Des. Test Comput., 2004)

Synthesis of skewed logic circuits. - Aiqun Cao; Naran Sirisantana; Cheng-Kok Koh; Kaushik Roy 001 (ACM Trans. Design Autom. Electr. Syst., 2005)