Rapid Prototyping of Reconfigurable Coprocessors. - Naren Narasimhan; Vinoo Srinivasan; Madhavi Vootukuru; Jeffrey Walrath; Sriram Govindarajan; Ranga Vemuri (ASAP, 1996)

Specification of Control Flow Properties for Verification of Synthesized VHDL Designs. - Naren Narasimhan; Ranga Vemuri (FMCAD, 1996)

Synchronous Controller Models for Synthesis from Communicating VHDL Processes. - Naren Narasimhan; Ranga Vemuri; Jay Roy (VLSI Design, 1996)

On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System. - Naren Narasimhan; Ranga Vemuri (TPHOLs, 1998)

Formal verification of the Pentium(R) 4 multiplier. - Roope Kaivola; Naren Narasimhan (HLDVT, 2001)

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis. - Naren Narasimhan; Elena Teica; Rajesh Radhakrishnan; Sriram Govindarajan; Ranga Vemuri (Formal Methods Syst. Des., 2001)

Formal Verification of the Pentium ® 4 Floating-Point Multiplier. - Roope Kaivola; Naren Narasimhan (DATE, 2002)

Reference model based RTL verification: an integrated approach. - William N. N. Hung; Naren Narasimhan (HLDVT, 2004)

Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation. - Roope Kaivola; Rajnish Ghughal; Naren Narasimhan; Amber Telfer; Jesse Whittemore; Sudhindra Pandav; Anna Slobodová; Christopher Taylor; Vladimir A. Frolov; Erik Reeber; Armaghan Naik (CAV, 2009)