A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. - Narender Hanchate; Nagarajan Ranganathan (VLSI Design, 2004)

LECTOR: a technique for leakage reduction in CMOS circuits. - Narender Hanchate; Nagarajan Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. - Narender Hanchate; Nagarajan Ranganathan (ISQED, 2006)

CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. - Nagarajan Ranganathan; Ravi Namballa; Narender Hanchate (ISVLSI, 2006)

A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. - Narender Hanchate; Nagarajan Ranganathan (VLSI Design, 2006)

Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. - Narender Hanchate; Nagarajan Ranganathan (IEEE Trans. Computers, 2006)

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. - Narender Hanchate; Nagarajan Ranganathan (ACM Trans. Design Autom. Electr. Syst., 2006)

Integrated Gate and Wire Sizing at Post Layout Level. - Narender Hanchate; Nagarajan Ranganathan (ISVLSI, 2007)

Statistical Gate Sizing for Yield Enhancement at Post Layout Level. - Narender Hanchate; Nagarajan Ranganathan (ISVLSI, 2007)

Improving Chip Design Performance and Productivity Using Machine Learning. - Narender Hanchate (ISPD, 2022)