Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. - Narendra Devta-Prasanna; Sudhakar M. Reddy; Arun Gunda; P. Krishnamurthy; Irith Pomeranz (Asian Test Symposium, 2005)

Should Illinois-Scan Based Architectures be Centralized or Distributed? - Ahmad A. Al-Yamani; Narendra Devta-Prasanna; Arun Gunda (DFT, 2005)

A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (ICCD, 2005)

Methods for improving transition delay fault coverage using broadside tests. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2005)

Test Generation for Open Defects in CMOS Circuits. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2006)

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (ETS, 2006)

Systematic Scan Reconfiguration. - Ahmad A. Al-Yamani; Narendra Devta-Prasanna; Arun Gunda (ASP-DAC, 2007)

Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. - Ahmad A. Al-Yamani; Narendra Devta-Prasanna; Erik Chmelar; M. Grinchuk; Arun Gunda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2008)

An Enhanced Logic BIST Architecture for Online Testing. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (IOLTS, 2008)

Detection of Internal Stuck-open Faults in Scan Chains. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2008)

On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (VTS, 2008)

Comparative study of centralised and distributed compatibility-based test data compression. - Ahmad A. Al-Yamani; Narendra Devta-Prasanna; Arun Gunda (IET Comput. Digit. Tech., 2008)

Detectability of internal bridging faults in scan chains. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (ASP-DAC, 2009)

Improving the Detectability of Resistive Open Faults in Scan Cells. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2009)

Accurate measurement of small delay defect coverage of test patterns. - Narendra Devta-Prasanna; Sandeep Kumar Goel; Arun Gunda; Mark Ward; P. Krishnamurthy (ITC, 2009)

Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study. - Sandeep Kumar Goel; Narendra Devta-Prasanna; Mark Ward (ITC, 2009)

Effective and Efficient Test Pattern Generation for Small Delay Defect. - Sandeep Kumar Goel; Narendra Devta-Prasanna; Ritesh P. Turakhia (VTS, 2009)

Clock Gate Test Points. - Narendra Devta-Prasanna; Arun Gunda (ITC, 2010)

Multiple fault activation cycle tests for transistor stuck-open faults. - Narendra Devta-Prasanna; Arun Gunda; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2010)

Silicon evaluation of faster than at-speed transition delay tests. - Sreejit Chakravarty; Narendra Devta-Prasanna; Arun Gunda; Junxia Ma; Fan Yang 060; H. Guo; R. Lai; D. Li (VTS, 2012)

A novel method for fast identification of peak current during test. - Wei Zhao 010; Sreejit Chakravarty; Junxia Ma; Narendra Devta-Prasanna; Fan Yang 060; Mohammad Tehranipoor (VTS, 2012)

Small-Delay Defect Coverage Metrics. - Narendra Devta-Prasanna; Sandeep Kumar Goel (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)

Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects. - Sandeep Kumar Goel; Narendra Devta-Prasanna (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)