SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. - Kevin Zhang 001; Uddalak Bhattacharya; Zhanping Chen; Fatih Hamzaoglu; Daniel Murray; Narendra Vallepalli; Yih Wang; Bo Zheng; Mark Bohr (IEEE J. Solid State Circuits, 2005)

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. - Kevin Zhang 001; Uddalak Bhattacharya; Zhanping Chen; Fatih Hamzaoglu; Daniel Murray; Narendra Vallepalli; Yih Wang; Bo Zheng; Mark Bohr (IEEE J. Solid State Circuits, 2006)