Parallel implementation of a 4*4-bit multiplier using a modified Booth's algorithm. - Naresh R. Shanbhag; Pushkal Juneja (IEEE J. Solid State Circuits, 1988)

Quaternary logic circuits in 2- mu m CMOS technology. - Naresh R. Shanbhag; Dipankar Nagchoudhuri; Raymond E. Siferd; Gangaikondan S. Visweswaran (IEEE J. Solid State Circuits, 1990)

An improved systolic architecture for 2-D digital filters. - Naresh R. Shanbhag (IEEE Trans. Signal Process., 1991)

A single-chip pipelined 2-D FIR filter using residue arithmetic. - Naresh R. Shanbhag; Raymond E. Siferd (IEEE J. Solid State Circuits, 1991)

Roundoff error analysis of the pipelined ADPCM coder. - Naresh R. Shanbhag; Keshab K. Parhi (ISCAS, 1993)

A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications. - Naresh R. Shanbhag; Keshab K. Parhi (ISCAS, 1993)

A pipelined adaptive lattice filter architecture. - Naresh R. Shanbhag; Keshab K. Parhi (IEEE Trans. Signal Process., 1993)

Pipelined Adaptive IIR Filter Architecture. - Naresh R. Shanbhag; Gi-Hong Im (ISCAS, 1995)

Pipelined adaptive DFE architectures using relaxed look-ahead. - Naresh R. Shanbhag; Keshab K. Parhi (IEEE Trans. Signal Process., 1995)

Low-power adaptive filter architectures via strength reduction. - Manish Goel; Naresh R. Shanbhag (ISLPED, 1996)

Lower bounds on power dissipation for DSP algorithms. - Naresh R. Shanbhag (ISLPED, 1996)

Pipelined adaptive IIR filter architectures using scattered and relaxed look-ahead transformations. - Naresh R. Shanbhag; Gi-Hong Im (IEEE Trans. Signal Process., 1996)

Analytical Estimation of Transition Activity From Word-Level Signal Statistics. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (DAC, 1997)

Achievable bounds on signal transition activity. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (ICCAD, 1997)

Dynamic algorithm transformation (DAT) for low-power adaptive signal processing. - Manish Goel; Naresh R. Shanbhag (ISLPED, 1997)

Analytical estimation of signal transition activity from word-level statistics. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN. - Naresh R. Shanbhag; Manish Goel (IEEE Trans. Signal Process., 1997)

Improving the throughput of flexible-precision DSPS via algorithm transformation. - Manoj Aggarwal; Naresh R. Shanbhag; Narendra Ahuja (ICASSP, 1998)

Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT). - Manish Goel; Naresh R. Shanbhag (ICASSP, 1998)

Energy-efficiency in presence of deep submicron noise. - Rajamohana Hegde; Naresh R. Shanbhag (ICCAD, 1998)

Decorrelating (DECOR) transformations for low-power adaptive filters. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (ISLPED, 1998)

Efficient wireless image transmission under a total power constraint. - Swaroop Appadwedula; Manish Goel; Douglas L. Jones; Kannan Ramchandran; Naresh R. Shanbhag (MMSP, 1998)

Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (VLSI Design, 1998)

Algorithms Transformation Techniques for Low-Power Wireless VLSI Systems Design. - Naresh R. Shanbhag (Int. J. Wirel. Inf. Networks, 1998)

Finite-precision analysis of the pipelined strength-reduced adaptive filter. - Manish Goel; Naresh R. Shanbhag (IEEE Trans. Signal Process., 1998)

A pipelined adaptive NEXT canceller. - Gi-Hong Im; Naresh R. Shanbhag (IEEE Trans. Signal Process., 1998)

VLSI systems design of 51.84 Mb/s transceivers for ATM-LAN and broadband access. - Naresh R. Shanbhag; Gi-Hong Im (IEEE Trans. Signal Process., 1998)

Low-power channel coding via dynamic reconfiguration. - Manish Goel; Naresh R. Shanbhag (ICASSP, 1999)

Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI. - Rajamohana Hegde; Naresh R. Shanbhag (ISCAS (6), 1999)

Low-power distributed arithmetic architectures using nonuniform memory partitioning. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (ISCAS (3), 1999)

Noise-tolerant dynamic circuit design. - Lei Wang 003; Naresh R. Shanbhag (ISCAS (1), 1999)

Energy-efficient dynamic circuit design in the presence of crosstalk noise. - Ganesh Balamurugan; Naresh R. Shanbhag (ISLPED, 1999)

Energy-efficient signal processing via algorithmic noise-tolerance. - Rajamohana Hegde; Naresh R. Shanbhag (ISLPED, 1999)

A low power data-adaptive motion estimation algorithm. - Jayanto Minocha; Naresh R. Shanbhag (MMSP, 1999)

Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. - Sudhakar Bobba; Ibrahim N. Hajj; Naresh R. Shanbhag (VLSI Design, 1999)

Dynamic algorithm transforms for low-power reconfigurable adaptive equalizers. - Manish Goel; Naresh R. Shanbhag (IEEE Trans. Signal Process., 1999)

A low-power phase-splitting adaptive equalizer for high bit-rate communication systems. - Rajamohana Hegde; Naresh R. Shanbhag (IEEE Trans. Signal Process., 1999)

Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing. - Manish Goel; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A coding framework for low-power address and data busses. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Information-theoretic bounds on average signal transition activity [VLSI systems]. - Sumant Ramprasad; Naresh R. Shanbhag; Ibrahim N. Hajj (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A noise-tolerant dynamic circuit design technique. - Ganesh Balamurugan; Naresh R. Shanbhag (CICC, 2000)

Algorithmic noise-tolerance for low-power signal processing in the deep submicron era. - Rajamohana Hegde; Naresh R. Shanbhag (EUSIPCO, 2000)

Low-power digital filtering via soft DSP. - Rajamohana Hegde; Naresh R. Shanbhag (ICASSP, 2000)

Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. - Ki-Wook Kim; Kwang-Hyun Baek; Naresh R. Shanbhag; C. L. Liu 001; Sung-Mo Kang (ICCAD, 2000)

Instruction scheduling for low power on dynamically variable voltage processors. - Mohammad M. Mansour; Makram M. Mansour; Ibrahim N. Hajj; Naresh R. Shanbhag (ICECS, 2000)

Low-power decimation filters for oversampling ADCs via the decorrelating (DECOR) transform. - Dongwon Seo; Naresh R. Shanbhag; Milton Feng (ISCAS, 2000)

Energy-efficiency bounds for noise-tolerant dynamic circuits. - Naresh R. Shanbhag; Lei Wang 003 (ISCAS, 2000)

Architecture driven filter transformations. - Manish Sharma; Naresh R. Shanbhag (ISCAS, 2000)

Reliable low-power design in the presence of deep submicron noise (embedded tutorial session). - Naresh R. Shanbhag; Krishnamurthy Soumyanath; Samuel Martin (ISLPED, 2000)

Toward achieving energy efficiency in presence of deep submicron noise. - Rajamohana Hegde; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Implementation of a Hermitian decoder IC in 0.35 μm CMOS. - Jonathan B. Ashbrook; Naresh R. Shanbhag; Ralf Koetter; Richard E. Blahut (CICC, 2001)

A low-power digital filter IC via soft DSP. - Rajamohana Hegde; Naresh R. Shanbhag (CICC, 2001)

Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers. - Lei Wang 003; Naresh R. Shanbhag (ISLPED, 2001)

The twin-transistor noise-tolerant dynamic circuit technique. - Ganesh Balamurugan; Naresh R. Shanbhag (IEEE J. Solid State Circuits, 2001)

Soft digital signal processing. - Rajamohana Hegde; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2001)

High-speed architectures for Reed-Solomon decoders. - Dilip V. Sarwate; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Total System Energy Minimization for Wireless Image Transmission. - Swaroop Appadwedula; Manish Goel; Naresh R. Shanbhag; Douglas L. Jones; Kannan Ramchandran (J. VLSI Signal Process., 2001)

Guest Editorial: Reconfigurable Signal Processing Systems. - Wayne P. Burleson; Naresh R. Shanbhag (J. VLSI Signal Process., 2001)

Reliable and energy-efficient digital signal processing. - Naresh R. Shanbhag (DAC, 2002)

Turbo decoder architectures for low-density parity-check codes. - Mohammad M. Mansour; Naresh R. Shanbhag (GLOBECOM, 2002)

Design methodology for high-speed iterative decoder architectures. - Mohammad M. Mansour; Naresh R. Shanbhag (ICASSP, 2002)

Simplified current and delay models for deep submicron CMOS digital circuits. - Mohammad M. Mansour; Naresh R. Shanbhag (ISCAS (5), 2002)

Low-power VLSI decoder architectures for LDPC codes. - Mohammad M. Mansour; Naresh R. Shanbhag (ISLPED, 2002)

A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. - Ram K. Krishnamurthy; Atila Alvandpour; Ganesh Balamurugan; Naresh R. Shanbhag; Krishnamurthy Soumyanath; Shekhar Y. Borkar (IEEE J. Solid State Circuits, 2002)

Analysis of linear turbo equalizer via EXIT chart. - Seok-Jun Lee; Andrew C. Singer; Naresh R. Shanbhag (GLOBECOM, 2003)

Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. - Ganesh Balamurugan; Naresh R. Shanbhag (ICCD, 2003)

High bandwidth transimpedance amplifier design using active transmission lines. - Hyeon-Min Bae; Naresh R. Shanbhag (ISCAS (1), 2003)

Architecture-aware low-density parity-check codes. - Mohammad M. Mansour; Naresh R. Shanbhag (ISCAS (2), 2003)

Performance analysis of algorithmic noise-tolerance techniques. - Byonghyo Shim; Naresh R. Shanbhag (ISCAS (4), 2003)

A low-power VLSI architecture for turbo decoding. - Seok-Jun Lee; Naresh R. Shanbhag; Andrew C. Singer (ISLPED, 2003)

Low-power filtering via adaptive error-cancellation. - Lei Wang 003; Naresh R. Shanbhag (IEEE Trans. Signal Process., 2003)

Complexity analysis of multicarrier and single-carrier systems for very high-speed digital subscriber line. - Byonghyo Shim; Naresh R. Shanbhag (IEEE Trans. Signal Process., 2003)

VLSI architectures for SISO-APP decoders. - Mohammad M. Mansour; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2003)

High-throughput LDPC decoders. - Mohammad M. Mansour; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise. - Lei Wang 003; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Low-power MIMO signal processing. - Lei Wang 003; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A communication-theoretic design paradigm for reliable SOCs. - Naresh R. Shanbhag (DAC, 2004)

Switching LMS linear turbo equalization. - Seok-Jun Lee; Andrew C. Singer; Naresh R. Shanbhag (ICASSP (4), 2004)

Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. - Srinivasa R. Sridhara; Arshad Ahmed; Naresh R. Shanbhag (ICCD, 2004)

Switching methods for linear turbo equalization. - Seok-Jun Lee; Naresh R. Shanbhag; Andrew C. Singer (ISCAS (3), 2004)

Reduced complexity interpolation for soft-decoding of reed-solomon codes. - Arshad Ahmed; Ralf Koetter; Naresh R. Shanbhag (ISIT, 2004)

Reliable and Efficient System-on-Chip Design. - Naresh R. Shanbhag (Computer, 2004)

A voltage overscaled low-power digital filter IC. - Rajamohana Hegde; Naresh R. Shanbhag (IEEE J. Solid State Circuits, 2004)

Reliable low-power digital signal processing via reduced precision redundancy. - Byonghyo Shim; Srinivasa R. Sridhara; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2004)

An energy-efficient circuit technique for single event transient noise-tolerance. - Ming Zhang 017; Naresh R. Shanbhag (ISCAS (1), 2005)

A low-power bus design using joint repeater insertion and coding. - Srinivasa R. Sridhara; Naresh R. Shanbhag (ISLPED, 2005)

Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. - Srinivasa R. Sridhara; Naresh R. Shanbhag (VLSI Design, 2005)

8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew. - James E. Jaussi; Ganesh Balamurugan; David R. Johnson; Bryan Casper; Aaron Martin; Joseph T. Kennedy; Naresh R. Shanbhag; Randy Mooney (IEEE J. Solid State Circuits, 2005)

A 285-MHz pipelined MAP decoder in 0.18-μm CMOS. - Seok-Jun Lee; Naresh R. Shanbhag; Andrew C. Singer (IEEE J. Solid State Circuits, 2005)

Linear turbo equalization analysis via BER transfer and EXIT charts. - Seok-Jun Lee; Andrew C. Singer; Naresh R. Shanbhag (IEEE Trans. Signal Process., 2005)

Area-efficient high-throughput MAP decoder architectures. - Seok-Jun Lee; Naresh R. Shanbhag; Andrew C. Singer (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Coding for system-on-chip networks: a unified framework. - Srinivasa R. Sridhara; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Energy Efficient VLSI Architecture for Linear Turbo Equalizer. - Seok-Jun Lee; Naresh R. Shanbhag; Andrew C. Singer (J. VLSI Signal Process., 2005)

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes. - Mohammad M. Mansour; Naresh R. Shanbhag (J. VLSI Signal Process., 2005)

Guest Editorial. - Naresh R. Shanbhag; Keshab K. Parhi (J. VLSI Signal Process., 2005)

Energy-efficient motion estimation using error-tolerance. - Girish Varatkar; Naresh R. Shanbhag (ISLPED, 2006)

An MLSE Receiver for Electronic Dispersion Compensation of OC-192 Fiber Links. - Hyeon-Min Bae; Jonathan B. Ashbrook; Jinki Park; Naresh R. Shanbhag; Andrew C. Singer; Sanjiv Chopra (IEEE J. Solid State Circuits, 2006)

A 640-Mb/s 2048-bit programmable LDPC decoder chip. - Mohammad M. Mansour; Naresh R. Shanbhag (IEEE J. Solid State Circuits, 2006)

Soft-Error-Rate-Analysis (SERA) Methodology. - Ming Zhang 017; Naresh R. Shanbhag (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Dual-Sampling Skewed CMOS Design for Soft-Error Tolerance. - Ming Zhang 017; Naresh R. Shanbhag (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Energy-efficient soft error-tolerant digital signal processing. - Byonghyo Shim; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Sequential Element Design With Built-In Soft Error Resilience. - Ming Zhang 017; Subhasish Mitra; T. M. Mak; Norbert Seifert; Nicholas J. Wang; Quan Shi; Kee Sup Kim; Naresh R. Shanbhag; Sanjay J. Patel (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Sensor Network-On-Chip. - Girish Varatkar; Sriram Narayanan; Naresh R. Shanbhag; Douglas L. Jones (SoC, 2007)

Variation-Tolerant Motion Estimation Architecture. - Girish Varatkar; Naresh R. Shanbhag (SiPS, 2007)

Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes. - Srinivasa R. Sridhara; Naresh R. Shanbhag (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Forward error correction for high-speed I/O. - Rajan Lakshmi Narasimha; Naresh R. Shanbhag (ACSCC, 2008)

Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip. - Girish Varatkar; Sriram Narayanan; Naresh R. Shanbhag; Douglas L. Jones (ACM Great Lakes Symposium on VLSI, 2008)

Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumption. - Shrikanth S. Narayanan; Girish Varatkar; Douglas L. Jones; Naresh R. Shanbhag (ICASSP, 2008)

Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC. - Girish Varatkar; Sriram Narayanan; Naresh R. Shanbhag; Douglas L. Jones (ISCAS, 2008)

Error-resilient low-power Viterbi decoders. - Rami A. Abdallah; Naresh R. Shanbhag (ISLPED, 2008)

A 10Gb/s MLSE-based Electronic-Dispersion-Compensation IC with Fast Power-Transient Management for WDM Add/Drop Networks. - Hyeon-Min Bae; Andrew C. Singer; Jonathan B. Ashbrook; Naresh R. Shanbhag (ISSCC, 2008)

Trends and Challenges in Optical Communications Front-End. - Yuriy M. Greshishchev; Takuji Yamamoto; Naresh R. Shanbhag (ISSCC, 2008)

Error-resilient low-power Viterbi decoders via state clustering. - Rami A. Abdallah; Naresh R. Shanbhag (SiPS, 2008)

The Search for Alternative Computational Paradigms. - Naresh R. Shanbhag; Subhasish Mitra; Gustavo de Veciana; Michael Orshansky; Radu Marculescu; Jaijeet S. Roychowdhury; Douglas L. Jones; Jan M. Rabaey (IEEE Des. Test Comput., 2008)

Fast Power Transient Management for OC-192 WDM Add/Drop Networks. - Hyeon-Min Bae; Jonathan B. Ashbrook; Naresh R. Shanbhag; Andrew C. Singer (IEEE J. Solid State Circuits, 2008)

Electronic dispersion compensation. - Andrew C. Singer; Naresh R. Shanbhag; Hyeon-Min Bae (IEEE Signal Process. Mag., 2008)

Joint Equalization and Coding for On-Chip Bus Communication. - Srinivasa R. Sridhara; Ganesh Balamurugan; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Error-Resilient Motion Estimation Architecture. - Girish Varatkar; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links. - Rajan Narasimha; Nirmal Warke; Naresh R. Shanbhag (GLOBECOM, 2009)

Soft NMR: Exploiting statistics for energy-efficiency. - Eric P. Kim; Rami A. Abdallah; Naresh R. Shanbhag (SoC, 2009)

Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes. - Rami A. Abdallah; Seok-Jun Lee; Manish Goel; Naresh R. Shanbhag (SiPS, 2009)

Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard. - Junho Cho; Naresh R. Shanbhag; Wonyong Sung (SiPS, 2009)

Error-resilient low-power Viterbi decoder architectures. - Rami A. Abdallah; Naresh R. Shanbhag (IEEE Trans. Signal Process., 2009)

Signal Processing for High-Speed Links. - Naresh R. Shanbhag; Andrew C. Singer; Hyeon-Min Bae (Handbook of Signal Processing Systems, 2010)

Stochastic computation. - Naresh R. Shanbhag; Rami A. Abdallah; Rakesh Kumar 002; Douglas L. Jones (DAC, 2010)

Soft NMR: Analysis & application to DSP systems. - Eric P. Kim; Naresh R. Shanbhag (ICASSP, 2010)

Robust and energy-efficient DSP systems via output probability processing. - Rami A. Abdallah; Naresh R. Shanbhag (ICCD, 2010)

BER-optimal analog-to-digital converters for communication links. - Minwei Lu; Naresh R. Shanbhag; Andrew C. Singer (ISCAS, 2010)

Transceiver circuits for optical communications. - Yuriy M. Greshishchev; Franz Dielacher; Michael Flynn; Donhee Ham; Naresh R. Shanbhag; Takuji Yamamoto (ISSCC, 2010)

Energy-efficient high-speed interfaces. - Naresh R. Shanbhag; Koichi Yamaguchi; Robert Payne (ISSCC, 2010)

Minimum-Energy Operation Via Error Resiliency. - Rami A. Abdallah; Naresh R. Shanbhag (IEEE Embed. Syst. Lett., 2010)

Design of Energy-Efficient High-Speed Links via Forward Error Correction. - Rajan Narasimha; Naresh R. Shanbhag (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Computation as estimation: a general framework for robustness and energy efficiency in SoCs. - Sriram Narayanan; Girish Varatkar; Douglas L. Jones; Naresh R. Shanbhag (IEEE Trans. Signal Process., 2010)

Stochastic Networked Computation. - Girish Varatkar; Shrikanth S. Narayanan; Naresh R. Shanbhag; Douglas L. Jones (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Low power and error resilient PN code acquisition filter via statistical error compensation. - Eric P. Kim; Daniel J. Baker; Sriram Narayanan; Douglas L. Jones; Naresh R. Shanbhag (CICC, 2011)

Timing error statistics for energy-efficient robust DSP systems. - Rami A. Abdallah; Yu-Hung Lee; Naresh R. Shanbhag (DATE, 2011)

System-assisted analog mixed-signal design. - Naresh R. Shanbhag; Andrew C. Singer (DATE, 2011)

Least squares approximation and polyphase decomposition for pipelining recursive filters. - Aditya Gupta; Andrew C. Singer; Naresh R. Shanbhag (ICASSP, 2011)

System energy minimization via joint optimization of the DC-DC converter and the core. - Rami A. Abdallah; Pradeep S. Shenoy; Naresh R. Shanbhag; Philip T. Krein (ISLPED, 2011)

An energy-efficient multiple-input multiple-output (MIMO) detector architecture. - Eric P. Kim; Naresh R. Shanbhag (SiPS, 2011)

VLSI Architectures for Soft-Decision Decoding of Reed-Solomon Codes. - Arshad Ahmed; Ralf Koetter; Naresh R. Shanbhag (IEEE Trans. Inf. Theory, 2011)

A sphere decoding approach for the vector Viterbi algorithm. - Peter Kairouz; Aolin Xu 001; Naresh R. Shanbhag; Andrew C. Singer (ACSCC, 2012)

A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation. - Rami A. Abdallah; Naresh R. Shanbhag (CICC, 2012)

FEC-based 4 Gb/s backplane transceiver in 90nm CMOS. - Adam C. Faust; Rajan Narasimha; Karan S. Bhatia; Ankit Srivastava; Chhay Kong; Hyeon-Min Bae; Elyse Rosenbaum; Naresh R. Shanbhag (CICC, 2012)

A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems. - Aadithya V. Karthik; Yingyan Lin; Chenjie Gu; Aolin Xu 001; Jaijeet S. Roychowdhury; Naresh R. Shanbhag (ICASSP, 2012)

System-driven metrics for the design and adaptation of analog to digital converters. - Rajan Narasimha; Georg Zeitler; Naresh R. Shanbhag; Andrew C. Singer; Gerhard Kramer (ICASSP, 2012)

Energy-Efficient LDPC Decoders Based on Error-Resiliency. - Eric P. Kim; Naresh R. Shanbhag (SiPS, 2012)

Soft N-Modular Redundancy. - Eric P. Kim; Naresh R. Shanbhag (IEEE Trans. Computers, 2012)

BER-Optimal Analog-to-Digital Converters for Communication Links. - Rajan Narasimha; Minwei Lu; Naresh R. Shanbhag; Andrew C. Singer (IEEE Trans. Signal Process., 2012)

Statistical analysis of algorithmic noise tolerance. - Eric P. Kim; Naresh R. Shanbhag (ICASSP, 2013)

Error-resilient systems via statistical signal processing. - Rami A. Abdallah; Naresh R. Shanbhag (SiPS, 2013)

Error resilient MRF message passing architecture for stereo matching. - Jungwook Choi; Eric P. Kim; Rob A. Rutenbar; Naresh R. Shanbhag (SiPS, 2013)

An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation. - Rami A. Abdallah; Naresh R. Shanbhag (IEEE J. Solid State Circuits, 2013)

Robust and Energy Efficient Multimedia Systems via Likelihood Processing. - Rami A. Abdallah; Naresh R. Shanbhag (IEEE Trans. Multim., 2013)

Signal Processing for High-Speed Links. - Naresh R. Shanbhag; Andrew C. Singer; Hyeon-Min Bae (Handbook of Signal Processing Systems, 2013)

Energy-efficient accelerator architecture for stereo image matching using approximate computing and statistical error compensation. - Eric P. Kim; Naresh R. Shanbhag (GlobalSIP, 2014)

Embedded error compensation for energy efficient DSP systems. - Sai Zhang; Naresh R. Shanbhag (GlobalSIP, 2014)

A robust message passing based stereo matching kernel via system-level error resiliency. - Eric P. Kim; Jungwook Choi; Naresh R. Shanbhag; Rob A. Rutenbar (ICASSP, 2014)

An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM. - Mingu Kong; Min-Sun Keel; Naresh R. Shanbhag; Sean Eilert; Ken Curewitz (ICASSP, 2014)

Space-time slicer architectures for analog-to-information conversion in channel equalizers. - Aseem Wadhwa; Upamanyu Madhow; Naresh R. Shanbhag (ICC, 2014)

Energy-efficient dot product computation using a switched analog circuit architecture. - Ihab Nahlus; Eric P. Kim; Naresh R. Shanbhag; David T. Blaauw (ISLPED, 2014)

A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS. - Sai Zhang; Jane S. Tu; Naresh R. Shanbhag; Philip T. Krein (IEEE J. Solid State Circuits, 2014)

System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near-Vt Computing. - Sai Zhang; Naresh R. Shanbhag; Philip T. Krein (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Reducing Energy at the Minimum Energy Operating Point Via Statistical Error Compensation. - Rami A. Abdallah; Naresh R. Shanbhag (IEEE Trans. Very Large Scale Integr. Syst., 2014)

An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks. - Mingu Kang; Sujan K. Gonugondla; Min-Sun Keel; Naresh R. Shanbhag (ICASSP, 2015)

Reduced Overhead Error Compensation for Energy Efficient Machine Learning Kernels. - Sai Zhang; Naresh R. Shanbhag (ICCAD, 2015)

Energy-efficient and high throughput sparse distributed memory architecture. - Mingu Kang; Eric P. Kim; Min-Sun Keel; Naresh R. Shanbhag (ISCAS, 2015)

Statistical information processing: Computing for the nanoscale era. - Naresh R. Shanbhag (ISLPED, 2015)

A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS. - Eric P. Kim; Daniel J. Baker; Sriram Narayanan; Naresh R. Shanbhag; Douglas L. Jones (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics. - Sai Zhang; Naresh R. Shanbhag (DATE, 2016)

Analysis of error resiliency of belief propagation in computer vision. - Jungwook Choi; Ameya D. Patil; Rob A. Rutenbar; Naresh R. Shanbhag (ICASSP, 2016)

Perfect error compensation via algorithmic error cancellation. - Sujan K. Gonugondla; Byonghyo Shim; Naresh R. Shanbhag (ICASSP, 2016)

Variation-Tolerant Architectures for Convolutional Neural Networks in the Near Threshold Voltage Regime. - Yingyan Lin; Sai Zhang; Naresh R. Shanbhag (SiPS, 2016)

A 481pJ/decision 3.4M decision/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array. - Mingu Kang; Sujan K. Gonugondla; Ameya Patil; Naresh R. Shanbhag (CoRR, 2016)

Understanding the Energy and Precision Requirements for Online Learning. - Charbel Sakr; Ameya Patil; Sai Zhang; Naresh R. Shanbhag (CoRR, 2016)

Energy-efficient Machine Learning in Silicon: A Communications-inspired Approach. - Naresh R. Shanbhag (CoRR, 2016)

Reducing the Energy Cost of Inference via In-sensor Information Processing. - Sai Zhang; Mingu Kang; Charbel Sakr; Naresh R. Shanbhag (CoRR, 2016)

Error-Resilient Machine Learning in Near Threshold Voltage via Classifier Ensemble. - Sai Zhang; Naresh R. Shanbhag (CoRR, 2016)

Correction to "An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation". - Rami A. Abdallah; Naresh R. Shanbhag (IEEE J. Solid State Circuits, 2016)

In-Memory Computing Architectures for Sparse Distributed Memory. - Mingu Kang; Naresh R. Shanbhag (IEEE Trans. Biomed. Circuits Syst., 2016)

A Study of BER-Optimal ADC-Based Receiver for Serial Links. - Yingyan Lin; Min-Sun Keel; Adam C. Faust; Aolin Xu 001; Naresh R. Shanbhag; Elyse Rosenbaum; Andrew C. Singer (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Embedded Algorithmic Noise-Tolerance for Signal Processing and Machine Learning Systems via Data Path Decomposition. - Sai Zhang; Naresh R. Shanbhag (IEEE Trans. Signal Process., 2016)

Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching. - Eric P. Kim; Jungwook Choi; Naresh R. Shanbhag; Rob A. Rutenbar (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. - Ameya Patil; Naresh R. Shanbhag; Lav R. Varshney; Eric Pop; H.-S. Philip Wong; Subhasish Mitra; Jan M. Rabaey; Jeffrey A. Weldon; Larry T. Pileggi; Sasikanth Manipatruni; Dmitri E. Nikonov; Ian A. Young (DAC, 2017)

A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array. - Mingu Kang; Sujan K. Gonugondla; Naresh R. Shanbhag (ESSCIRC, 2017)

Minimum precision requirements for the SVM-SGD learning algorithm. - Charbel Sakr; Ameya D. Patil; Sai Zhang; Yongjune Kim 001; Naresh R. Shanbhag (ICASSP, 2017)

Analytical Guarantees on Numerical Precision of Deep Neural Networks. - Charbel Sakr; Yongjune Kim 001; Naresh R. Shanbhag (ICML, 2017)

PredictiveNet: An energy-efficient convolutional neural network via zero prediction. - Yingyan Lin; Charbel Sakr; Yongjune Kim 001; Naresh R. Shanbhag (ISCAS, 2017)

Shannon-inspired Statistical Computing to Enable Spintronics. - Ameya D. Patil; Sasikanth Manipatruni; Dmitri E. Nikonov; Ian A. Young; Naresh R. Shanbhag (CoRR, 2017)

Slicer Architectures for Analog-to-Information Conversion in Channel Equalizers. - Aseem Wadhwa; Upamanyu Madhow; Naresh R. Shanbhag (IEEE Trans. Commun., 2017)

Minimum Precision Requirements for Deep Learning with Biomedical Datasets. - Charbel Sakr; Naresh R. Shanbhag (BioCAS, 2018)

True Gradient-Based Training of Deep Binary Activated Neural Networks Via Continuous Binarization. - Charbel Sakr; Jungwook Choi; Zhuo Wang; Kailash Gopalakrishnan; Naresh R. Shanbhag (ICASSP, 2018)

An Analytical Method to Determine Minimum Per-Layer Precision of Deep Neural Networks. - Charbel Sakr; Naresh R. Shanbhag (ICASSP, 2018)

PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms. - Prakalp Srivastava; Mingu Kang; Sujan K. Gonugondla; Sungmin Lim; Jungwook Choi; Vikram S. Adve; Nam Sung Kim; Naresh R. Shanbhag (ISCA, 2018)

Energy-Efficient Deep In-memory Architecture for NAND Flash Memories. - Sujan K. Gonugondla; Mingu Kang; Yongjune Kim 001; Mark Helm; Sean Eilert; Naresh R. Shanbhag (ISCAS, 2018)

SRAM Bit-line Swings Optimization using Generalized Waterfilling. - Yongjune Kim 001; Mingu Kang; Lav R. Varshney; Naresh R. Shanbhag (ISIT, 2018)

A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training. - Sujan Kumar Gonugondla; Mingu Kang; Naresh R. Shanbhag (ISSCC, 2018)

An In-Memory VLSI Architecture for Convolutional Neural Networks. - Mingu Kang; Sungmin Lim; Sujan K. Gonugondla; Naresh R. Shanbhag (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training. - Sujan K. Gonugondla; Mingu Kang; Naresh R. Shanbhag (IEEE J. Solid State Circuits, 2018)

A 19.4-nJ/Decision, 364-K Decisions/s, In-Memory Random Forest Multi-Class Inference Accelerator. - Mingu Kang; Sujan K. Gonugondla; Sungmin Lim; Naresh R. Shanbhag (IEEE J. Solid State Circuits, 2018)

A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array. - Mingu Kang; Sujan K. Gonugondla; Ameya Patil; Naresh R. Shanbhag (IEEE J. Solid State Circuits, 2018)

Generalized Water-Filling for Source-Aware Energy-Efficient SRAMs. - Yongjune Kim 001; Mingu Kang; Lav R. Varshney; Naresh R. Shanbhag (IEEE Trans. Commun., 2018)

A Rank Decomposed Statistical Error Compensation Technique for Robust Convolutional Neural Networks in the Near Threshold Voltage Regime. - Yingyan Lin; Sai Zhang; Naresh R. Shanbhag (J. Signal Process. Syst., 2018)

Per-Tensor Fixed-Point Quantization of the Back-Propagation Algorithm. - Charbel Sakr; Naresh R. Shanbhag (ICLR (Poster), 2019)

Accumulation Bit-Width Scaling For Ultra-Low Precision Training Of Deep Networks. - Charbel Sakr; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Ankur Agrawal; Naresh R. Shanbhag; Kailash Gopalakrishnan (ICLR (Poster), 2019)

An MRAM-Based Deep In-Memory Architecture for Deep Neural Networks. - Ameya D. Patil; Haocheng Hua; Sujan K. Gonugondla; Mingu Kang; Naresh R. Shanbhag (ISCAS, 2019)

An Energy-Efficient Classifier via Boosted Spin Channel Networks. - Ameya D. Patil; Sasikanth Manipatruni; Dmitri E. Nikonov; Ian A. Young; Naresh R. Shanbhag (ISCAS, 2019)

Minimum Precision Requirements of General Margin Hyperplane Classifiers. - Charbel Sakr; Yongjune Kim 001; Naresh R. Shanbhag (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

Efficient Local Secret Sharing for Distributed Blockchain Systems. - Yongjune Kim 001; Ravi Kiran Raman; Young-Sik Kim; Lav R. Varshney; Naresh R. Shanbhag (IEEE Commun. Lett., 2019)

An Energy-Efficient Programmable Mixed-Signal Accelerator for Machine Learning Algorithms. - Mingu Kang; Prakalp Srivastava; Vikram S. Adve; Nam Sung Kim; Naresh R. Shanbhag (IEEE Micro, 2019)

Shannon-Inspired Statistical Computing for the Nanoscale Era. - Naresh R. Shanbhag; Naveen Verma; Yongjune Kim 001; Ameya D. Patil; Lav R. Varshney (Proc. IEEE, 2019)

KeyRAM: A 0.34 uJ/decision 18 k decisions/s Recurrent Attention In-memory Processor for Keyword Spotting. - Hassan Dbouk; Sujan K. Gonugondla; Charbel Sakr; Naresh R. Shanbhag (CICC, 2020)

DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. - Hassan Dbouk; Hetul Sanghvi; Mahesh Mehendale; Naresh R. Shanbhag (ECCV (27), 2020)

Low-Complexity Fixed-Point Convolutional Neural Networks For Automatic Target Recognition. - Hassan Dbouk; Hanfei Geng; Craig M. Vineyard; Naresh R. Shanbhag (ICASSP, 2020)

SWIPE: Enhancing Robustness of ReRAM Crossbars for In-memory Computing. - Sujan K. Gonugondla; Ameya D. Patil; Naresh R. Shanbhag (ICCAD, 2020)

Fundamental Limits on the Precision of In-memory Architectures. - Sujan K. Gonugondla; Charbel Sakr; Hassan Dbouk; Naresh R. Shanbhag (ICCAD, 2020)

HarDNN: Feature Map Vulnerability Evaluation in CNNs. - Abdulrahman Mahmoud; Siva Kumar Sastry Hari; Christopher W. Fletcher; Sarita V. Adve; Charbel Sakr; Naresh R. Shanbhag; Pavlo Molchanov 001; Michael B. Sullivan 001; Timothy Tsai 002; Stephen W. Keckler (CoRR, 2020)

Nanotechnology-inspired Information Processing Systems of the Future. - Randy Bryant; Mark D. Hill; Tom Kazior; Daniel Lee; Jie Liu; Klara Nahrstedt; Vijay Narayanan; Jan M. Rabaey; Hava T. Siegelmann; Naresh R. Shanbhag; Naveen Verma; H.-S. Philip Wong (CoRR, 2020)

Deep In-Memory Architectures in SRAM: An Analog Approach to Approximate Computing. - Mingu Kang; Sujan K. Gonugondla; Naresh R. Shanbhag (Proc. IEEE, 2020)

Deep In-Memory Architectures for Machine Learning-Accuracy Versus Efficiency Trade-Offs. - Mingu Kang; Yongjune Kim 001; Ameya D. Patil; Naresh R. Shanbhag (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

SE1: What Technologies Will Shape the Future of Computing? - Hugh Mair; Shinichiro Shiratake; Eric Karl; Thomas Burd; Jonathan Chang; Debbie Marr; Samuel Naffziger; Henk Corporaal; Ken Takeuchi; Naresh R. Shanbhag (ISSCC, 2021)

Optimizing Selective Protection for CNN Resilience. - Abdulrahman Mahmoud; Siva Kumar Sastry Hari; Christopher W. Fletcher; Sarita V. Adve; Charbel Sakr; Naresh R. Shanbhag; Pavlo Molchanov 001; Michael B. Sullivan 001; Timothy Tsai 002; Stephen W. Keckler (ISSRE, 2021)

Generalized Depthwise-Separable Convolutions for Adversarially Robust and Efficient Neural Networks. - Hassan Dbouk; Naresh R. Shanbhag (NeurIPS, 2021)

Robustifying 𝓁∞ Adversarial Training to the Union of Perturbation Models. - Ameya D. Patil; Michael Tuttle; Alexander G. Schwing; Naresh R. Shanbhag (CoRR, 2021)

A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting. - Hassan Dbouk; Sujan K. Gonugondla; Charbel Sakr; Naresh R. Shanbhag (IEEE J. Solid State Circuits, 2021)

Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures. - Charbel Sakr; Naresh R. Shanbhag (IEEE Trans. Signal Process., 2021)

Comprehending In-memory Computing Trends via Proper Benchmarking. - Naresh R. Shanbhag; Saion K. Roy (CICC, 2022)

IMPQ: Reduced Complexity Neural Networks Via Granular Precision Assignment. - Sujan Kumar Gonugondla; Naresh R. Shanbhag (ICASSP, 2022)

Adversarial Vulnerability of Randomized Ensembles. - Hassan Dbouk; Naresh R. Shanbhag (ICML, 2022)

Fundamental Limits on the Computational Accuracy of Resistive Crossbar-based In-memory Architectures. - Saion K. Roy; Ameya Patil; Naresh R. Shanbhag (ISCAS, 2022)

Coordinated Science Laboratory 70th Anniversary Symposium: The Future of Computing. - Klara Nahrstedt; Naresh R. Shanbhag; Vikram S. Adve; Nancy M. Amato; Romit Roy Choudhury; Carl A. Gunter; Nam Sung Kim; Olgica Milenkovic; Sayan Mitra; Lav R. Varshney; Yurii Vlasov; Sarita V. Adve; et al. (CoRR, 2022)

Fundamental Limits on Energy-Delay-Accuracy of In-Memory Architectures in Inference Applications. - Sujan K. Gonugondla; Charbel Sakr; Hassan Dbouk; Naresh R. Shanbhag (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. - Wangxin He; Jian Meng; Sujan Kumar Gonugondla; Shimeng Yu; Naresh R. Shanbhag; Jae-sun Seo (DATE, 2023)

Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation. - Saion K. Roy; Han-Mo Ou; Mostafa Gamal Ahmed; Peter Deaville; Bonan Zhang; Naveen Verma; Pavan Kumar Hanumolu; Naresh R. Shanbhag (ESSCIRC, 2023)

Boosting the Accuracy of SRAM-Based in-Memory Architectures Via Maximum Likelihood-Based Error Compensation Method. - Hyungyo Kim; Naresh R. Shanbhag (ICASSP, 2023)

Enhancing the Accuracy of Resistive In-Memory Architectures using Adaptive Signal Processing. - Han-Mo Ou; Naresh R. Shanbhag (ICASSP, 2023)

On the Robustness of Randomized Ensembles to Adversarial Perturbations. - Hassan Dbouk; Naresh R. Shanbhag (ICML, 2023)

On the Security Vulnerabilities of MRAM-based In-Memory Computing Architectures against Model Extraction Attacks. - Saion K. Roy; Naresh R. Shanbhag (ICCAD, 2024)

Enhancing the Accuracy of 6T SRAM-Based In-Memory Architecture via Maximum Likelihood Detection. - Hyungyo Kim; Naresh R. Shanbhag (IEEE Trans. Signal Process., 2024)

Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation. - Saion K. Roy; Han-Mo Ou; Mostafa Gamal Ahmed; Peter Deaville; Bonan Zhang; Naveen Verma; Pavan Kumar Hanumolu; Naresh R. Shanbhag (IEEE J. Solid State Circuits, 2025)