A gridless multi-layer area router. - Naresh Sehgal; C. Y. Roger Chen; John M. Acken (Great Lakes Symposium on VLSI, 1994)

An object-oriented cell library manager. - Naresh Sehgal; C. Y. Roger Chen; John M. Acken (ICCAD, 1994)

Power conscious CAD tools and methodologies: a perspective. - Deo Singh; Jan M. Rabaey; Massoud Pedram; Francky Catthoor; Suresh Rajgopal; Naresh Sehgal; Thomas J. Mozdzen (Proc. IEEE, 1995)

A general approach for regularity extraction in datapath circuits. - Amit Chowdhary; Sudhakar Kale; Phani K. Saripella; Naresh Sehgal; Rajesh K. Gupta 001 (ICCAD, 1998)

Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations. - Bharat Krishna; C. Y. Roger Chen; Naresh Sehgal (VLSI Design, 1998)

GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs. - Bülent Basaran; Kiran Ganesh; Raymond Y. K. Lau; Artour Levin; Miles McCoo; Srinivasan Rangarajan; Naresh Sehgal (VLSI Design, 1999)

Extraction of functional regularity in datapath circuits. - Amit Chowdhary; Sudhakar Kale; Phani K. Saripella; Naresh Sehgal; Rajesh K. Gupta 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A sensitivity based placer for standard cells. - Bill Halpin; C. Y. Roger Chen; Naresh Sehgal (ACM Great Lakes Symposium on VLSI, 2000)

A novel technique for sea of gates global routing. - Bharat Krishna; C. Y. Roger Chen; Naresh Sehgal (ACM Great Lakes Symposium on VLSI, 2000)

Timing Driven Placement using Physical Net Constraints. - Bill Halpin; C. Y. Roger Chen; Naresh Sehgal (DAC, 2001)

A novel ultra-fast heuristic for VLSI CAD steiner trees. - Bharat Krishna; C. Y. Roger Chen; Naresh Sehgal (ACM Great Lakes Symposium on VLSI, 2003)

Detailed Placement with Net Length Constraints. - Bill Halpin; Naresh Sehgal; C. Y. Roger Chen (IWSOC, 2003)