An Efficient Self-Transposing Memory Structure for 32-bit Video Processors. - Mahdi Nazm Bojnordi; Naser Sedaghati-Mokhtari; Omid Fatemi; Mahmoud Reza Hashemi (APCCAS, 2006)

A High-Speed Low-Complexity VLSI SISO Architecture. - M. Nabipoor; S. A. Khodaian; Naser Sedaghati-Mokhtari; Sied Mehdi Fakhraie; Seyed Hamaidreza Jamali (APCCAS, 2006)

Power efficient sequential multiplication using pre-computation. - Nima Honarmand; M. Reza Javaheri; Naser Sedaghati-Mokhtari; Ali Afzali-Kusha (ISCAS, 2006)

Simulation of Voice Processing Applications through VLIW DSP Architectures. - Naser Sedaghati-Mokhtari; Mahdi Nazm Bojnordi; Amin Farmahini Farahani; Mahmoud Mousavinezhad; Sied Mehdi Fakhraie (ICECS, 2007)

MDST: Multiprocessor DSP Simulation Toolkit for Voice Processing Applications. - Naser Sedaghati-Mokhtari; Mahdi Nazm Bojnordi; Sied Mehdi Fakhraie (MASCOTS, 2007)

An Efficient and Extendable Modeling Approach for VLIW DSP Processors. - Naser Sedaghati-Mokhtari; Mahdi Nazm Bojnordi; Abbas Hormati; Sied Mehdi Fakhraie (CSICC, 2008)

StVEC: A Vector Instruction Extension for High Performance Stencil Computation. - Naser Sedaghati; Renji Thomas; Louis-Noël Pouchet; Radu Teodorescu; P. Sadayappan (PACT, 2011)

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips. - Timothy N. Miller; Xiang Pan; Renji Thomas; Naser Sedaghati; Radu Teodorescu (HPCA, 2012)

An efficient two-dimensional blocking strategy for sparse matrix-vector multiplication on GPUs. - Arash Ashari; Naser Sedaghati; John Eisenlohr; P. Sadayappan (ICS, 2014)

Fast Sparse Matrix-Vector Multiplication on GPUs for Graph Applications. - Arash Ashari; Naser Sedaghati; John Eisenlohr; Srinivasan Parthasarathy 001; P. Sadayappan (SC, 2014)

On Using the Roofline Model with Lower Bounds on Data Movement. - Venmugil Elango; Naser Sedaghati; Fabrice Rastello; Louis-Noël Pouchet; J. Ramanujam; Radu Teodorescu; P. Sadayappan (ACM Trans. Archit. Code Optim., 2014)

Automatic Selection of Sparse Matrix Representation on GPUs. - Naser Sedaghati; Te Mu; Louis-Noël Pouchet; Srinivasan Parthasarathy 001; P. Sadayappan (ICS, 2015)

A model-driven blocking strategy for load balanced sparse matrix-vector multiplication on GPUs. - Arash Ashari; Naser Sedaghati; John Eisenlohr; P. Sadayappan (J. Parallel Distributed Comput., 2015)

Core tunneling: Variation-aware voltage noise mitigation in GPUs. - Renji Thomas; Kristin Barber; Naser Sedaghati; Li Zhou 012; Radu Teodorescu (HPCA, 2016)

EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures. - Renji Thomas; Naser Sedaghati; Radu Teodorescu (ISPASS, 2016)

Adaptive Time-based Encoding for Energy-Efficient Large Cache Architectures. - Payman Behnam; Naser Sedaghati; Mahdi Nazm Bojnordi (E2SC@SC, 2017)