A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor. - Nasser A. Kurd; Javed S. Barkatullah; Rommel O. Dizon; Thomas D. Fletcher; Paul D. Madland (IEEE J. Solid State Circuits, 2001)

A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. - Muhammad M. Khellah; Maged Ghoneima; James W. Tschanz; Yibin Ye; Nasser A. Kurd; Javed Barkatullah; Srikanth Nimmagadda; Yehea I. Ismail (ICCD, 2005)

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. - James W. Tschanz; Nam-Sung Kim; Saurabh Dighe; Jason Howard; Gregory Ruhl; Sriram R. Vangal; Siva G. Narendra; Yatin Hoskote; Howard Wilson; Carol Lam; Matthew Shuman; Carlos Tokunaga; et al. (ISSCC, 2007)

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. - Maged Ghoneima; Muhammad M. Khellah; James W. Tschanz; Yibin Ye; Nasser A. Kurd; Javed Barkatullah; Srikanth Nimmagadda; Yehea I. Ismail; Vivek K. De (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking. - Nasser A. Kurd; Praveen Mosalikanti; Mark Neidengard; Jonathan Douglas; Rajesh Kumar (IEEE J. Solid State Circuits, 2009)

Westmere: A family of 32nm IA processors. - Nasser A. Kurd; Subramani Bhamidipati; Christopher Mozak; Jeffrey L. Miller; Timothy M. Wilson; Mahadev Nemani; Muntaquim Chowdhury (ISSCC, 2010)

A Family of 32 nm IA Processors. - Nasser A. Kurd; Subramani Bhamidipati; Christopher Mozak; Jeffrey L. Miller; Praveen Mosalikanti; Timothy M. Wilson; Ali M. El-Husseini; Mark Neidengard; Ramy E. Aly; Mahadev Nemani; Muntaquim Chowdhury; Rajesh Kumar (IEEE J. Solid State Circuits, 2011)

Modeling the response of Bang-Bang digital PLLs to phase error perturbations. - Moataz Abdelfattah; Maged Ghoneima; Yehea I. Ismail; Amr Lotfy; Mohamed Abdel-moneum; Nasser A. Kurd; Greg Taylor (CICC, 2012)

A novel digital loop filter architecture for bang-bang ADPLL. - Moataz Abdelfattah; Maged Ghoneima; Yehea I. Ismail; Amr Lotfy; Mohamed Abdelsalam; Mohamed Abdel-moneum; Nasser A. Kurd; Greg Taylor (SoCC, 2012)

Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm. - Nasirul Chowdhury; Jeff Wight; Christopher Mozak; Nasser A. Kurd (VLSI-DAT, 2012)

5.9 Haswell: A family of IA 22nm processors. - Nasser A. Kurd; Muntaquim Chowdhury; Edward Burton; Thomas P. Thomas; Christopher Mozak; Brent Boswell; Manoj Lal; Anant Deval; Jonathan Douglas; Ali M. El-Husseini; Ankireddy Nalamalpu; Timothy M. Wilson; et al. (ISSCC, 2014)

A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. - Amr Lotfy; Syed Feruz Syed Farooq; Qi S. Wang; Soner Yaldiz; Praveen Mosalikanti; Nasser A. Kurd (CICC, 2015)

Low power analog circuit techniques in the 5th generation intel coreTM microprocessor (broadwell). - Praveen Mosalikanti; Nasser A. Kurd; Christopher Mozak; Takao Oshita (CICC, 2015)

Broadwell: A family of IA 14nm processors. - Ankireddy Nalamalpu; Nasser A. Kurd; Anant Deval; Christopher Mozak; Jonathan Douglas; Ashish Khanna; Fabrice Paillet; Gerhard Schrom; Boyd Phelps (VLSIC, 2015)

Haswell: A Family of IA 22 nm Processors. - Nasser A. Kurd; Muntaquim Chowdhury; Edward Burton; Thomas P. Thomas; Christopher Mozak; Brent Boswell; Praveen Mosalikanti; Mark Neidengard; Anant Deval; Ashish Khanna; Nasirul Chowdhury; Ravi Rajwar; et al. (IEEE J. Solid State Circuits, 2015)

19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS. - Kuan-Yueh James Shen; Syed Feruz Syed Farooq; Yongping Fan; Khoa Minh Nguyen; Qi Wang; Amr Elshazly; Nasser A. Kurd (ISSCC, 2016)

A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process. - Takao Oshita; Joseph Shor; David E. Duarte; Avner Kornfeld; George L. Geannopoulos; Jonathan Douglas; Nasser A. Kurd (IEEE J. Solid State Circuits, 2016)

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS. - Kuan-Yueh James Shen; Syed Feruz Syed Farooq; Yongping Fan; Khoa Minh Nguyen; Qi Wang; Mark Neidengard; Nasser A. Kurd; Amr Elshazly (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS. - Hao Luo; Somnath Kundu; Chun C. Lee; Rinkle Jain; Sarah Shahraini; Eduardo Alban; Timo Huusari; Jason Mix; Nasser A. Kurd; Mohamed Abdel-moneum; Brent R. Carlton (CICC, 2021)

29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop Mitigation. - Praveen Mosalikanti; Qi Wang; Kuan-Yueh James Shen; Mark Neidengard; Syed Feruz Syed Farooq; Vaughn Grossnickle; Nasser A. Kurd (ISSCC, 2021)

A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup. - Somnath Kundu; Timo Huusari; Hao Luo; Abhishek Agrawal; Eduardo Alban; Sarah Shahraini; Thao Xiong; Dan Lake; Stefano Pellerano; Jason Mix; Nasser A. Kurd; Mohamed Abdel-moneum; et al. (ISSCC, 2022)

Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. - Chi-Hsiang Huang 001; Yidong Chen 005; Xun Sun; Arindam Mandal; Venkata Rajesh Pamula 001; Nasser A. Kurd; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2022)

A Fast Startup Crystal Oscillator Using Impedance Guided Chirp Injection in 22 nm FinFET CMOS. - Hao Luo; Somnath Kundu; Timo Huusari; Sarah Shahraini; Eduardo Alban; Jason Mix; Nasser A. Kurd; Mohamed Abdel-Moneum; Brent R. Carlton (IEEE J. Solid State Circuits, 2022)

8.7 A Dual VDD-Temperature Sensor Employing Sensor Fusion with 2.4°C, 9mV (±3σ) Inaccuracy in 65nm CMOS. - Hikmet Seha Ozturk; Julian Arenas; Carlos Tokunaga; Nasser A. Kurd; Visvesh Sathe 001 (ISSCC, 2025)