Optimizing Parametric BIST Using Bio-inspired Computing Algorithms. - Nastaran Nemati; Amirhossein Simjour; Amirali Ghofrani; Zainalabedin Navabi (DFT, 2009)

Virtual tester development using HDL/PLI. - Arezoo Kamran; Nastaran Nemati; Somayeh Sadeghi Kohan; Zainalabedin Navabi (EWDTS, 2010)

A mixed HDL/PLI test package. - Nastaran Nemati; Majid Namaki-Shoushtari; Zainalabedin Navabi (EWDTS, 2010)

Near optimal machine learning based random test generation. - Niki Shakeri; Nastaran Nemati; Majid Nili Ahmadabadi; Zainalabedin Navabi (EWDTS, 2010)

Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing. - Nastaran Nemati; Zainalabedin Navabi (Asian Test Symposium, 2011)

Asynchronous test hardware for Null Convention Logic. - Nastaran Nemati; Mark C. Reed; Michael R. Frater (ISCAS, 2014)

Asynchronous interleaved scan architecture for on-line built-in self-test of null convention logic. - Nastaran Nemati; Mark C. Reed; Karl M. Fant; Paul Beckett (ISCAS, 2016)

Self-timed automatic test pattern generation for null convention logic. - Nastaran Nemati; Mark C. Reed; Sri Parameswaran; Karl M. Fant (MWSCAS, 2016)

Test and Testability of Asynchronous Circuits. - Nastaran Nemati (2017)

Clock-Less DFT-Less Test Strategy for Null Convention Logic. - Nastaran Nemati; Paul Beckett; Mark C. Reed; Karl M. Fant (IEEE Trans. Emerg. Top. Comput., 2018)