Scheduling Coarse-Grain Operations for VLIW Processors. - Natalino G. Busá; Albert van der Werf; Marco Bekooij (ISSS, 2000)

Functional units with conditional input/output behavior in VLIW processors. - Marco Bekooij; Loek J. M. Engels; Albert van der Werf; Natalino G. Busá (DATE, 2001)

Synthesizing A Long Latency Unit Within Vliw Processor. - Ram Lakhan Gupta; Anshul Kumar; Aalbert Van Der Werf; Natalino G. Busá (VLSI Design, 2001)

A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor. - Carles Rodoreda Sala; Natalino G. Busá (ISSS, 2002)

RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs. - Natalino G. Busá; Ghiath Alkadi; Michael J. Verberne; Rafael Peset Llopis; Sethuraman Ramanatha (IEEE International Workshop on Rapid System Prototyping, 2002)

C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems. - André Nieuwland; Jeffrey Kang; Om Prakash Gangwal; Ramanathan Sethuraman; Natalino G. Busá; Kees Goossens; Rafael Peset Llopis; Paul E. R. Lippens (Des. Autom. Embed. Syst., 2002)

Reconfigurable Instruction-Set Application-Tuning for DSP. - Bart Mesman; Qin Zhao; Natalino G. Busá; Katarzyna Leijten-Nowak (J. Circuits Syst. Comput., 2003)