ESD Reliability Challenges for RF/Mixed Signal Design & Processing. - Natarajan Mahadeva Iyer; M. K. Radhakrishnan (VLSI Design, 2003)

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS. - Dimitri Linten; Steven Thijs; Mahadeva Iyer Natarajan; Piet Wambacq; Wutthinan Jeamsaksiri; Javier Ramos; Abdelkarim Mercha; Snezana Jenei; Stéphane Donnay; Stefaan Decoutere (IEEE J. Solid State Circuits, 2005)

Introduction to special section on selected papers from EOS/ESD Symposium 2004. - Natarajan Mahadeva Iyer (Microelectron. Reliab., 2006)

Methodology to achieve planar technology-like ESD performance in FINFET process. - Jian-Hsing Lee; Manjunatha Prabhu; Konstantin Korablev; Jagar Singh; Mahadeva Iyer Natarajan; Shesh Mani Pandey (IRPS, 2015)

Printed-circuit board (PCB) charge induced product yield-loss during the final test. - Jian-Hsing Lee; Kunihiko Takahashi; Manjunatha Prabhu; Mahadeva Iyer Natarajan (IRPS, 2015)

Tunable Holding-Voltage High Voltage ESD Devices. - Jian-Hsing Lee; Natarajan Mahadeva Iyer (IRPS, 2019)

Physical Model for ESD Human Body Model to Transmission Line Pulse. - Jian-Hsing Lee; Natarajan Mahadeva Iyer; Timothy J. Maloney (IRPS, 2019)