A 12 MHz data cycle 4 Mb DRAM with pipeline operation. - Natsuki Kushiyama; Yohji Watanabe; Takashi Ohsawa; Kazuyoshi Muraoka; Yousei Nagahama; Tohru Furuyama (IEEE J. Solid State Circuits, 1991)

A 500-megabyte/s data-rate 4.5 M DRAM. - Natsuki Kushiyama; Shigeo Ohshima; Don Stark 001; Hiroyuki Noji; Kiyofumi Sakurai; Satoru Takase; Torhu Furuyama; Richard M. Barth; Andy Chan; John Dillon; James A. Gasbarro; Matthew M. Griffin; et al. (IEEE J. Solid State Circuits, 1993)

An experimental 295 MHz CMOS 4K⨉256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers. - Natsuki Kushiyama; Charles Tan; Richard Clark; Jane Lin; Fred Perner; Lisa Martin; Mark Leonard; Gene Coussens; Kit Cham (IEEE J. Solid State Circuits, 1995)

A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme. - Satoru Takase; Natsuki Kushiyama (IEEE J. Solid State Circuits, 1999)

A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver. - Osamu Hirabayashi; Atsushi Kawasumi; Azuma Suzuki; Yasuhisa Takeyama; Keiichi Kushida; Takahiko Sasaki; Akira Katayama; Gou Fukano; Yuki Fujimura; Takaaki Nakazato; Yasushi Shizuki; Natsuki Kushiyama; et al. (ISSCC, 2009)