120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs. - Yasushi Terada; Kazuo Kobayashi; Takeshi Nakayama; Masanori Hayashikoshi; Yoshikazu Miyawaki; Natsuo Ajika; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1989)

A 60-ns 16-Mb flash EEPROM with program and erase sequence controller. - Takeshi Nakayama; Shin'ichi Kobayashi; Yoshikazu Miyawaki; Yasushi Terada; Natsuo Ajika; Makoto Ohi; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara; Kimio Suzuki (IEEE J. Solid State Circuits, 1991)

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories. - Yoshikazu Miyawaki; Takeshi Nakayama; Shin'ichi Kobayashi; Natsuo Ajika; Makoto Ohi; Yasushi Terada; Hideaki Arima; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1992)

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. - Shin'ichi Kobayashi; Hiroaki Nakai; Yuichi Kunori; Takeshi Nakayama; Yoshikazu Miyawaki; Yasushi Terada; Hiroshi Onoda; Natsuo Ajika; Masahiro Hatanaka; Hirokazu Miyoshi; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1994)

A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications. - Atsushi Nozoe; Hiroaki Kotani; Tetsuya Tsujikawa; Keiichi Yoshida; Kazunori Furusawa; Masataka Kato; Toshiaki Nishimoto; Hitoshi Kume; Hideaki Kurata; Naoki Miyamoto; Shoji Kubono; Michitaro Kanamitsu; et al. (IEEE J. Solid State Circuits, 1999)

A 58-nm 2-Gb MLC "B4-Flash" Memory with Flexible Multisector Architecture. - Taku Ogura; Yasushi Kasa; Kazuhide Kurosaki; Mitsuhiro Tomoeda; Hisakazu Otoi; Satoshi Shimizu; Masafumi Katsumata; Natsuo Ajika; Kazuo Kobayashi (IEEE J. Solid State Circuits, 2017)