Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS. - Kosuke Furuichi; Hiromu Uemura; Natsuyuki Koda; Hiromi Inaba; Keiji Kishine (ISOCC, 2016)

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector. - Keiji Kishine; Hiroshi Inoue; Kosuke Furuichi; Natsuyuki Koda; Hiromu Uemura; Hiromi Inaba; Makoto Nakamura; Akira Tsuchiya (ISOCC, 2016)

Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system. - Natsuyuki Koda; Kosuke Furuichi; Hiromu Uemura; Hiromi Inaba; Keiji Kishine (ISOCC, 2016)

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. - Tomonori Tanaka; Kosuke Furuichi; Hiromu Uemura; Ryosuke Noguchi; Natsuyuki Koda; Koki Arauchi; Daichi Omoto; Hiromi Inaba; Keiji Kishine; Shinsuke Nakano; Masafumi Nogawa; Hideyuki Nosaka (ISCAS, 2017)

FPGA-based transceiver circuit for labeling signal transmission system. - Kohei Nomura; Natsuyuki Koda; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2017)