A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints. - Nattawut Thepayasuwan; Alex Doboli (IWLS, 2002)

Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip. - Nattawut Thepayasuwan; Vaishali Damle; Alex Doboli (ICCD, 2003)

An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications. - Nattawut Thepayasuwan; Hua Tang; Alex Doboli (ISCAS (5), 2003)

Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip. - Nattawut Thepayasuwan; Alex Doboli (DATE, 2004)

Hardware-Software Co-Design of Resource Constrained Systems on a Chip. - Nattawut Thepayasuwan; Alex Doboli (ICDCS Workshops, 2004)

OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip. - Nattawut Thepayasuwan; Alex Doboli (ISVLSI, 2004)

A continuous time markov decision process based on-chip buffer allocation methodology. - Sankalp Kallakuri; Nattawut Thepayasuwan; Alex Doboli; Eugene A. Feinberg (ACM Great Lakes Symposium on VLSI, 2005)

Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies. - Sankalp Kallakuri; Nattawut Thepayasuwan; Alex Doboli; Simona Doboli (ISCAS (2), 2005)

Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed. - Nattawut Thepayasuwan; Alex Doboli (IEEE Trans. Very Large Scale Integr. Syst., 2005)