A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. - Xun Sun; Sung Kim; Fahim ur Rahman; Venkata Rajesh Pamula 001; Xi Li; Naveen John; Visvesh S. Sathe 001 (ISSCC, 2018)

An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. - Fahim ur Rahman; Sung Kim; Naveen John; Roshan Kumar; Xi Li; Rajesh Pamula 001; Keith A. Bowman; Visvesh S. Sathe 001 (VLSI Circuits, 2018)

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. - Fahim ur Rahman; Sung Kim; Naveen John; Roshan Kumar; Xi Li; Rajesh Pamula 001; Keith A. Bowman; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2019)

An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. - Xun Sun; Fahim ur Rahman; Venkata Rajesh Pamula 001; Sung Kim; Xi Li; Naveen John; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2019)

Provably Secure Data Sharing Approach for Personal Health Records in Cloud Storage Using Session Password, Data Access Key, and Circular Interpolation. - Naveen John; I. Shatheesh Sam (Int. J. Semantic Web Inf. Syst., 2021)