Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. - Rajeev Balasubramonian; Naveen Muralimanohar; Karthik Ramani; Venkatanand Venkatachalapathy (HPCA, 2005)

Interconnect-Aware Coherence Protocols for Chip Multiprocessors. - Liqun Cheng; Naveen Muralimanohar; Karthik Ramani; Rajeev Balasubramonian; John B. Carter (ISCA, 2006)

Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. - Naveen Muralimanohar; Karthik Ramani; Rajeev Balasubramonian (ISPASS, 2006)

Leveraging Wire Properties at the Microarchitecture Level. - Rajeev Balasubramonian; Naveen Muralimanohar; Karthik Ramani; Liqun Cheng; John B. Carter (IEEE Micro, 2006)

Interconnect design considerations for large NUCA caches. - Naveen Muralimanohar; Rajeev Balasubramonian (ISCA, 2007)

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. - Naveen Muralimanohar; Rajeev Balasubramonian; Norman P. Jouppi (MICRO, 2007)

Scalable and reliable communication for hardware transactional memory. - Seth H. Pugsley; Manu Awasthi; Niti Madan; Naveen Muralimanohar; Rajeev Balasubramonian (PACT, 2008)

Architecting Efficient Interconnects for Large Caches with CACTI 6.0. - Naveen Muralimanohar; Rajeev Balasubramonian; Norman P. Jouppi (IEEE Micro, 2008)

Non-uniform power access in large caches with low-swing wires. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian (HiPC, 2009)

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. - Niti Madan; Li Zhao 002; Naveen Muralimanohar; Aniruddha N. Udipi; Rajeev Balasubramonian; Ravishankar R. Iyer 001; Srihari Makineni; Donald Newell (HPCA, 2009)

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. - Xiangyu Dong 001; Naveen Muralimanohar; Norman P. Jouppi; Richard Kaufmann; Yuan Xie 001 (SC, 2009)

Wire Aware Cache Architecture. - Naveen Muralimanohar (2009)

Towards scalable, energy-efficient, bus-based on-chip networks. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian (HPCA, 2010)

Rethinking DRAM design and organization for energy-constrained multi-cores. - Aniruddha N. Udipi; Naveen Muralimanohar; Niladrish Chatterjee; Rajeev Balasubramonian; Al Davis; Norman P. Jouppi (ISCA, 2010)

Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. - Xiangyu Dong 001; Yuan Xie 001; Naveen Muralimanohar; Norman P. Jouppi (SC, 2010)

CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study. - Jung Ho Ahn; Raymond G. Beausoleil; Nathan L. Binkert; Al Davis; Marco Fiorentino; Norman P. Jouppi; Moray McLaren; Matteo Monchiero; Naveen Muralimanohar; Robert Schreiber; Dana Vantrease (Low Power Networks-on-Chip, 2011)

FREE-p: Protecting non-volatile memory against both hard and soft errors. - Doe Hyun Yoon; Naveen Muralimanohar; Jichuan Chang; Parthasarathy Ranganathan; Norman P. Jouppi; Mattan Erez (HPCA, 2011)

The role of optics in future high radix switch design. - Nathan L. Binkert; Al Davis; Norman P. Jouppi; Moray McLaren; Naveen Muralimanohar; Robert Schreiber; Jung Ho Ahn (ISCA, 2011)

Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian; Al Davis; Norman P. Jouppi (ISCA, 2011)

System implications of memory reliability in exascale computing. - Sheng Li 007; Ke Chen 020; Ming-yu Hsieh; Naveen Muralimanohar; Chad D. Kersey; Jay B. Brockman; Arun F. Rodrigues; Norman P. Jouppi (SC, 2011)

Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. - Xiangyu Dong 001; Yuan Xie 001; Naveen Muralimanohar; Norman P. Jouppi (ACM Trans. Archit. Code Optim., 2011)

Multi-Core Cache Hierarchies - Rajeev Balasubramonian; Norman P. Jouppi; Naveen Muralimanohar (Morgan & Claypool Publishers, 2011)

CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. - Ke Chen 020; Sheng Li 007; Naveen Muralimanohar; Jung Ho Ahn; Jay B. Brockman; Norman P. Jouppi (DATE, 2012)

Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. - Niladrish Chatterjee; Naveen Muralimanohar; Rajeev Balasubramonian; Al Davis; Norman P. Jouppi (HPCA, 2012)

LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. - Aniruddha N. Udipi; Naveen Muralimanohar; Rajeev Balasubramonian; Al Davis; Norman P. Jouppi (ISCA, 2012)

BOOM: Enabling mobile memory based low-power server DIMMs. - Doe Hyun Yoon; Jichuan Chang; Naveen Muralimanohar; Parthasarathy Ranganathan (ISCA, 2012)

Design trade-offs for high density cross-point resistive memory. - Dimin Niu; Cong Xu 002; Naveen Muralimanohar; Norman P. Jouppi; Yuan Xie 001 (ISLPED, 2012)

Optical High Radix Switch Design. - Nathan L. Binkert; Al Davis; Norman P. Jouppi; Moray McLaren; Naveen Muralimanohar; Robert Schreiber; Jung Ho Ahn (IEEE Micro, 2012)

Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism. - Doe Hyun Yoon; Naveen Muralimanohar; Jichuan Chang; Parthasarathy Ranganathan; Norman P. Jouppi; Mattan Erez (IEEE Micro, 2012)

Understanding the trade-offs in multi-level cell ReRAM memory design. - Cong Xu 002; Dimin Niu; Naveen Muralimanohar; Norman P. Jouppi; Yuan Xie 001 (DAC, 2013)

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. - Dimin Niu; Cong Xu 002; Naveen Muralimanohar; Norman P. Jouppi; Yuan Xie 001 (ICCAD, 2013)

Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories. - HanBin Yoon; Justin Meza; Naveen Muralimanohar; Norman P. Jouppi; Onur Mutlu (ACM Trans. Archit. Code Optim., 2014)

Overcoming the challenges of crossbar resistive memory architectures. - Cong Xu 002; Dimin Niu; Naveen Muralimanohar; Rajeev Balasubramonian; Tao Zhang 032; Shimeng Yu; Yuan Xie 001 (HPCA, 2015)

Improving memristor memory with sneak current sharing. - Manjunath Shevgoor; Naveen Muralimanohar; Rajeev Balasubramonian; Yoocharn Jeon (ICCD, 2015)

History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. - Ke Chen 020; Sheng Li 007; Jung Ho Ahn; Naveen Muralimanohar; Jishen Zhao; Cong Xu 002; Seongil O; Yuan Xie 001; Jay B. Brockman; Norman P. Jouppi (ICS, 2015)

CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models. - Norman P. Jouppi; Andrew B. Kahng; Naveen Muralimanohar; Vaishnav Srinivas (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Enabling technologies for memory compression: Metadata, mapping, and prediction. - Arjun Deb; Paolo Faraboschi; Ali Shafiee; Naveen Muralimanohar; Rajeev Balasubramonian; Robert Schreiber (ICCD, 2016)

ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. - Ali Shafiee; Anirban Nag; Naveen Muralimanohar; Rajeev Balasubramonian; John Paul Strachan; Miao Hu 002; R. Stanley Williams; Vivek Srikumar (ISCA, 2016)

Near-Memory Data Services. - Babak Falsafi; Mircea Stan; Kevin Skadron; Nuwan Jayasena; Yunji Chen; Jinhua Tao; Ravi Nair; Jaime H. Moreno; Naveen Muralimanohar; Karthikeyan Sankaralingam; Cristian Estan (IEEE Micro, 2016)

CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories. - Rajeev Balasubramonian; Andrew B. Kahng; Naveen Muralimanohar; Ali Shafiee; Vaishnav Srinivas (ACM Trans. Archit. Code Optim., 2017)

Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. - Anirban Nag; Ali Shafiee; Rajeev Balasubramonian; Vivek Srikumar; Naveen Muralimanohar (CoRR, 2018)

Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. - Anirban Nag; Rajeev Balasubramonian; Vivek Srikumar; Ross Walker 001; Ali Shafiee; John Paul Strachan; Naveen Muralimanohar (IEEE Micro, 2018)