Hierarchical fault modeling for analog and mixed-signal circuits. - Naveena Nagi; Jacob A. Abraham (VTS, 1992)

Delay fault testing of iterative arithmetic arrays. - Rabindra K. Roy; Naveena Nagi; Abhijit Chatterjee; Manuel A. d'Abreu (VTS, 1992)

DRAFTS: Discretized Analog Circuit Fault Simulator. - Naveena Nagi; Abhijit Chatterjee; Jacob A. Abraham (DAC, 1993)

Fault-based automatic test generator for linear analog circuits. - Naveena Nagi; Abhijit Chatterjee; Ashok Balivada; Jacob A. Abraham (ICCAD, 1993)

MIXER: Mixed-Signal Fault Simulator. - Naveena Nagi; Abhijit Chatterjee; Jacob A. Abraham (ICCD, 1993)

Fault simulation of linear analog circuits. - Naveena Nagi; Abhijit Chatterjee; Jacob A. Abraham (J. Electron. Test., 1993)

A Signature Analyzer for Analog and Mixed-signal Circuits. - Naveena Nagi; Abhijit Chatterjee; Jacob A. Abraham (ICCD, 1994)

Efficient multisine testing of analog circuits. - Naveena Nagi; Abhijit Chatterjee; Ashok Balivada; Jacob A. Abraham (VLSI Design, 1995)

Low-cost DC built-in self-test of linear analog circuits using checksums. - Abhijit Chatterjee; Bruce C. Kim; Naveena Nagi (VLSI Design, 1996)

DC Built-In Self-Test for Linear Analog Circuits. - Abhijit Chatterjee; Bruce C. Kim; Naveena Nagi (IEEE Des. Test Comput., 1996)

A unified approach for fault simulation of linear mixed-signal circuits. - Ashok Balivada; Hong Zheng; Naveena Nagi; Abhijit Chatterjee; Jacob A. Abraham (J. Electron. Test., 1996)

A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST. - Stephen K. Sunter; Naveena Nagi (ITC, 1997)

Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. - Abhijit Chatterjee; Naveena Nagi (VLSI Design, 1997)

Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. - Pramodchandran N. Variyam; Abhijit Chatterjee; Naveena Nagi (VTS, 1997)

Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits. - Heebyung Yoon; Pramodchandran N. Variyam; Abhijit Chatterjee; Naveena Nagi (VTS, 1998)

Signature analysis for analog and mixed-signal circuit test response compaction. - Naveena Nagi; Abhijit Chatterjee; Heebyung Yoon; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Test Metrics for Analog Parametric Faults. - Stephen K. Sunter; Naveena Nagi (VTS, 1999)