Low-leakage asymmetric-cell SRAM. - Navid Azizi; Farid N. Najm; Andreas Moshovos (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Reconfigurable Molecular Dynamics Simulator. - Navid Azizi; Ian Kuon; Aaron Egier; Ahmad Darabiha; Paul Chow (FCCM, 2004)

FPGA-based supercomputing: an implementation for molecular dynamics. - Ian Kuon; Navid Azizi; Ahmad Darabiha; Aaron Egier; Paul Chow (FPGA, 2004)

An Asymmetric SRAM Cell to Lower Gate Leakage. - Navid Azizi; Farid N. Najm (ISQED, 2004)

Look-up table leakage reduction for FPGAs. - Navid Azizi; Farid N. Najm (CICC, 2005)

Variations-aware low-power design with voltage scaling. - Navid Azizi; Muhammad M. Khellah; Vivek De; Farid N. Najm (DAC, 2005)

A Case for Asymmetric-Cell Cache Memories. - Andreas Moshovos; Babak Falsafi; Farid N. Najm; Navid Azizi (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme. - Kostas Pagiamtzis; Navid Azizi; Farid N. Najm (CICC, 2006)

A family of cells to reduce the soft-error-rate in ternary-CAM. - Navid Azizi; Farid N. Najm (DAC, 2006)

An adaptive FPGA architecture with process variation compensation and reduced leakage. - Georges Nabaa; Navid Azizi; Farid N. Najm (DAC, 2006)

Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. - Khaled R. Heloue; Navid Azizi; Farid N. Najm (DAC, 2007)

Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. - Navid Azizi; Muhammad M. Khellah; Vivek De; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation. - Khaled R. Heloue; Navid Azizi; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

An intelligent approach to predict gas compressibility factor using neural network model. - Navid Azizi; Mashallah Rezakazemi; Mohammad Mehdi Zarei (Neural Comput. Appl., 2019)