Performance analysis of carbon nanotube interconnects for VLSI applications. - Navin Srivastava; Kaustav Banerjee (ICCAD, 2005)

A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. - Sheng-Chih Lin; Navin Srivastava; Kaustav Banerjee (ICCD, 2005)

Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. - Navin Srivastava; Xiaoning Qi; Kaustav Banerjee (ISQED, 2005)

Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. - Kaustav Banerjee; Sheng-Chih Lin; Navin Srivastava (ASP-DAC, 2006)

Introspective 3D chips. - Shashidhar Mysore; Banit Agrawal; Navin Srivastava; Sheng-Chih Lin; Kaustav Banerjee; Timothy Sherwood (ASPLOS, 2006)

Are carbon nanotubes the future of VLSI interconnections? - Kaustav Banerjee; Navin Srivastava (DAC, 2006)

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. - Gian Luca Loi; Banit Agrawal; Navin Srivastava; Sheng-Chih Lin; Timothy Sherwood; Kaustav Banerjee (DAC, 2006)

Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections? - Kaustav Banerjee; Sungjun Im; Navin Srivastava (Nano-Net, 2006)

3D Integration for Introspection. - Shashidhar Mysore; Banit Agrawal; Navin Srivastava; Sheng-Chih Lin; Kaustav Banerjee; Timothy Sherwood (IEEE Micro, 2007)

High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. - Navin Srivastava; Roberto Suaya; Kaustav Banerjee (DATE, 2008)

Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. - Navin Srivastava; Roberto Suaya; Kaustav Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. - Navin Srivastava; Roberto Suaya; Kaustav Banerjee (DATE, 2010)

Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. - Navin Srivastava; Chuan Xu; Roberto Suaya; Kaustav Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. - Chuan Xu; Navin Srivastava; Roberto Suaya; Kaustav Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)