A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults. - Navya Mohan; J. P. Anita (Int. J. Math. Model. Numer. Optimisation, 2016)

Efficient test scheduling for reusable BIST in 3D stacked ICs. - Navya Mohan; Maya Krishnan; Sudhir Kumar Rai; M. MathuMeitha; S. Sivakalyan (ICACCI, 2017)

Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults. - Navya Mohan; J. P. Anita (Integr., 2022)

Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model. - Navya Mohan; J. P. Anita (Cryptogr., 2023)