Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. - Kwen-Siong Chong; Aparna Shreedhar; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Chao Wang 096; Jun Zhou 017; Bah-Hwee Gwee; Joseph S. Chang (AsianHOST, 2019)

Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. - Aparna Shreedhar; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; L. Nalangilli; Wei Shu; Joseph S. Chang; Bah-Hwee Gwee (ISCAS, 2019)

High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC. - Weng-Geng Ho; Chuan-Seng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Bah-Hwee Gwee (APCCAS, 2020)

A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. - Weng-Geng Ho; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Jun-Sheng Ng; Juncheng Chen; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2020)

A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES). - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee (ISCAS, 2020)

Normalized Differential Power Analysis - for Ghost Peaks Mitigation. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Zhiping Lin 001; Joseph Sylvester Chang; Bah-Hwee Gwee (ISCAS, 2021)

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation. - Kwen-Siong Chong; Jun-Sheng Ng; Juncheng Chen; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Joseph Sylvester Chang; Bah-Hwee Gwee (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Incremental Linear Regression Attack. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Zhili Zou; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (AsianHOST, 2022)

Non-profiling based Correlation Optimization Deep Learning Analysis. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Zhiping Lin 001; Joseph Sylvester Chang; Bah-Hwee Gwee (ISCAS, 2022)

An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee (ISCAS, 2022)

Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs. - Jun-Sheng Ng; Juncheng Chen; Si Wu; Nay Aung Kyaw; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (ISCAS, 2023)

A Novel Non-profiling Side-Channel Attack on Masked Devices with Connectivity Matrix. - Juncheng Chen; Han Zhang; Zishuo Yang; Yicheng Xu; Nay Aung Kyaw; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (ISCAS, 2024)

Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine. - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Kwen-Siong Chong; Bah-Hwee Gwee (IEEE Trans. Very Large Scale Integr. Syst., 2024)

N-MUX: Neighborhood-Based Logic Locking Against Machine Learning Attacks. - Han Zhang; Xuenong Hong; Shirui Sheng; Juncheng Chen; Nay Aung Kyaw; Kwen-Siong Chong; Zhiping Lin 001; Bah-Hwee Gwee (ISCAS, 2025)