A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. - Nazanin Mansouri; Ranga Vemuri (FMCAD, 1998)

Automatic data path abstraction for verification of large scale designs. - Viresh Paruthi; Nazanin Mansouri; Ranga Vemuri (ICCD, 1998)

Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. - Nazanin Mansouri; Ranga Vemuri (DATE, 1999)

Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs. - Nazanin Mansouri; Ranga Vemuri (Formal Methods Syst. Des., 2000)

Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs. - Suleyman Tosun; Hakduran Koc; Nazanin Mansouri (VLSI, 2003)

Exploiting OVL standard assertions in a theorem-proving-based verification environment. - Anli He; Parija Sule; Youngsik Kim; Nazanin Mansouri (Circuits, Signals, and Systems, 2004)

Enhancing scheduling solutions through ant colony optimization. - Shekhar Kopuri; Nazanin Mansouri (ISCAS (5), 2004)

Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD). - Youngsik Kim; Shekhar Kopuri; Nazanin Mansouri (ISQED, 2004)

Reliability-Centric High-Level Synthesis. - Suleyman Tosun; Nazanin Mansouri; Ercument Arvas; Mahmut T. Kandemir; Yuan Xie 001 (DATE, 2005)

Exploiting PSL standard assertions in a theorem-proving-based verification environment. - Youngsik Kim; Parija Sule; Nazanin Mansouri (ACM Great Lakes Symposium on VLSI, 2005)

Reliability-Centric Hardware/Software Co-Design. - Suleyman Tosun; Nazanin Mansouri; Ercument Arvas; Mahmut T. Kandemir; Yuan Xie 001; Wei-Lun Hung (ISQED, 2005)

An ILP Formulation for Reliability-Oriented High-Level Synthesis. - Suleyman Tosun; Ozcan Ozturk 001; Nazanin Mansouri; Ercument Arvas; Mahmut T. Kandemir; Yuan Xie 001; Wei-Lun Hung (ISQED, 2005)

Constraint-based Code mapping for heterogeneous Chip multiprocessors. - Suleyman Tosun; Nazanin Mansouri; Mahmut T. Kandemir; Özcan Özturk 001 (SoCC, 2005)

Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits. - Shweta Shah; Nazanin Mansouri; Adrián Núñez-Aldana (CONIELECOMP, 2006)

An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors. - Suleyman Tosun; Nazanin Mansouri; Mahmut T. Kandemir; Ozcan Ozturk 001 (ISCIS, 2006)

Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron. - Deniz Dal; Adrian Nunez; Nazanin Mansouri (ISQED, 2006)

A high-level register optimization technique for minimizing leakage and dynamic power. - Deniz Dal; Nazanin Mansouri (ACM Great Lakes Symposium on VLSI, 2007)

Automated formal verification of scheduling with speculative code motions. - Youngsik Kim; Nazanin Mansouri (ACM Great Lakes Symposium on VLSI, 2008)

Determining the Optimal Number of Islands in Power Islands Synthesis. - Deniz Dal; Nazanin Mansouri (ISVLSI, 2008)

Power Optimization With Power Islands Synthesis. - Deniz Dal; Nazanin Mansouri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)