An all-digital clock and data recovery circuit for low-to-moderate data rate applications. - Ndiogou Tall; Nicolas Dehaese; Sylvain Bourdel; B. Bonat (ICECS, 2011)

Low-power clock and data recovery circuit for IR-UWB receiver power management. - Ndiogou Tall; Nicolas Dehaese; Sylvain Bourdel; Olivier Fourquin; Rémy Vauché; Jean Gaubert (SSD, 2012)

A Fully Differential 7.2-8.5GHz LNA for a Self Synchronized and Duty-Cycled UWB OOK Receiver. - I. Benamor; Ndiogou Tall; Nicolas Dehaese; Jean Gaubert; Sylvain Bourdel; Rémy Vauché; O. Ramos Sparrow; Stéphane Meillére (ICUWB, 2015)

Simulation and validation of arbitrary ordered VSCP-PLLs using event-driven macromodeling. - Ehsan Ali; Wenceslas Rahajandraibe; Fayrouz Haddad; Ndiogou Tall; Christian Hangmann; Christian Hedayat (ISCAS, 2015)

Exact and approximated discrete-time non-linear models of voltage switched CP-PLL. - Ehsan Ali; Wenceslas Rahajandraibe; Fayrouz Haddad; Ndiogou Tall; Christian Hangmann; Christian Hedayat (MWSCAS, 2015)

Modeling & PVT characterization of arbitrary ordered VSCP-PLL using an efficient event-driven approach. - Ehsan Ali; Wenceslas Rahajandraibe; Ndiogou Tall; Fayrouz Haddad; Christian Hangmann; Christian Hedayat (NEWCAS, 2015)

Ultra-wideband voltage controlled oscillator with commutable phases for BPSK implementation. - Remy Vauche; Eloi Muhr; Ndiogou Tall; Abderrahmane Haloua; Sylvain Bourdel; Jean Gaubert; Nicolas Dehaese; Hervé Barthélemy (NEWCAS, 2015)