A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang; Ne Kyaw Zwa Lwin (ISIC, 2014)

Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process. - Joseph S. Chang; Kwen-Siong Chong; Wei Shu; Tong Lin 001; Jize Jiang; Ne Kyaw Zwa Lwin; Yang Kang (MWSCAS, 2014)

High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). - Weng-Geng Ho; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2015)

Success rate model for fully AES-128 in correlation power analysis. - Ali Akbar Pammu; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Nan Liu 002; Bah-Hwee Gwee (APCCAS, 2016)

High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. - Weng-Geng Ho; Nan Liu 002; Kyaw Zwa Lwin Ne; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2016)

Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM. - Weng-Geng Ho; Kyaw Zwa Lwin Ne; N. Prashanth Srinivas; Kwen-Siong Chong; Tony Tae-Hyoung Kim; Bah-Hwee Gwee (ISCAS, 2016)

Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process. - Jize Jiang; Wei Shu; Kwen-Siong Chong; Tong Lin 001; Ne Kyaw Zwa Lwin; Joseph Sylvester Chang; Jingyuan Liu (ISCAS, 2016)

Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process. - Tong Lin 001; Kwen-Siong Chong; Wei Shu; Ne Kyaw Zwa Lwin; Jize Jiang; Joseph S. Chang (ISCAS, 2016)

Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack. - Weng-Geng Ho; Ali Akbar Pammu; Nan Liu 002; Kyaw Zwa Lwin Ne; Kwen-Siong Chong; Bah-Hwee Gwee (ISIC, 2016)

Single-Event-Transient Resilient Memory for DSP in Space Applications. - Ne Kyaw Zwa Lwin; H. Sivaramakrishnan; Kwen-Siong Chong; Tong Lin 001; Wei Shu; Joseph S. Chang (DSP, 2018)

Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. - Weng-Geng Ho; Kwen-Siong Chong; Kyaw Zwa Lwin Ne; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. - Kwen-Siong Chong; Aparna Shreedhar; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Chao Wang 096; Jun Zhou 017; Bah-Hwee Gwee; Joseph S. Chang (AsianHOST, 2019)

Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. - Aparna Shreedhar; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; L. Nalangilli; Wei Shu; Joseph S. Chang; Bah-Hwee Gwee (ISCAS, 2019)

Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications. - Weng-Geng Ho; Ali Akbar Pammu; Kyaw Zwa Lwin Ne; Kwen-Siong Chong; Bah-Hwee Gwee (SoCC, 2019)

A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor. - Ali Akbar Pammu; Weng-Geng Ho; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Bah-Hwee Gwee (IEEE Trans. Inf. Forensics Secur., 2019)

High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC. - Weng-Geng Ho; Chuan-Seng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Bah-Hwee Gwee (APCCAS, 2020)

Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller. - Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Wei Shu; Joseph S. Chang (ISCAS, 2020)

A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. - Weng-Geng Ho; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Jun-Sheng Ng; Juncheng Chen; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2020)

A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES). - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee (ISCAS, 2020)

High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications. - Weng-Geng Ho; Ali Akbar Pammu; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Bah-Hwee Gwee (ISOCC, 2020)

Normalized Differential Power Analysis - for Ghost Peaks Mitigation. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Zhiping Lin 001; Joseph Sylvester Chang; Bah-Hwee Gwee (ISCAS, 2021)

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation. - Kwen-Siong Chong; Jun-Sheng Ng; Juncheng Chen; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Joseph Sylvester Chang; Bah-Hwee Gwee (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Non-profiling based Correlation Optimization Deep Learning Analysis. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Zhiping Lin 001; Joseph Sylvester Chang; Bah-Hwee Gwee (ISCAS, 2022)

An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee (ISCAS, 2022)

A Novel Multi-Error-Lock-Trace (MELT) Test Structure for SET/SEU Characterization of Radiation-Hardened-By-Design Cells. - Rouli Fang; Kwen-Siong Chong; Kyaw Zwa Lwin Ne; Wei Shu; Sun-Yang Tay; Joseph Sylvester Chang (MWSCAS, 2024)