CAERUS: an effective arbitration and ejection policy for routing in an unidirectional torus. - Nihar Rathod; Shankar Balachandran; Neel Gala (INA-OCMC@HiPEAC, 2014)

ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. - Neel Gala; V. R. Devanathan; Karthik Srinivasan; V. Visvanathan; V. Kamakoti 001 (VLSID, 2014)

SHAKTI-F: A Fault Tolerant Microprocessor Architecture. - Sukrat Gupta; Neel Gala; G. S. Madhusudan; V. Kamakoti 001 (ATS, 2015)

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. - Neel Gala; V. R. Devanathan; V. Visvanathan; V. Kamakoti 001 (J. Low Power Electron., 2015)

STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection. - Neel Gala; Swagath Venkataramani; Anand Raghunathan; V. Kamakoti 001 (ISLPED, 2016)

ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance. - Vikas Chauhan; Neel Gala; V. Kamakoti 001 (VLSID, 2016)

SHAKTI Processors: An Open-Source Hardware Initiative. - Neel Gala; Arjun Menon; Rahul Bodduna; G. S. Madhusudan; V. Kamakoti 001 (VLSID, 2016)

ELENA: A low-cost portable electronic nose for alcohol characterization. - Subadra Murugan; Neel Gala (IEEE SENSORS, 2017)

Shakti-T: A RISC-V Processor with Light Weight Security Extensions. - Arjun Menon; Subadra Murugan; Chester Rebeiro; Neel Gala; Kamakoti Veezhinathan (HASP@ISCA, 2017)

A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks. - Arnab Roy 003; Swagath Venkataramani; Neel Gala; Sanchari Sen; Kamakoti Veezhinathan; Anand Raghunathan (ISLPED, 2017)

Approximate Error Detection With Stochastic Checkers. - Neel Gala; Swagath Venkataramani; Anand Raghunathan; V. Kamakoti 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators. - Neel Gala; Sarada Krithivasan; Wei-Yu Tsai; Xueqing Li 002; Vijaykrishnan Narayanan; V. Kamakoti 001 (ACM J. Emerg. Technol. Comput. Syst., 2018)

PERI: A Posit Enabled RISC-V Core. - Sugandha Tiwari; Neel Gala; Chester Rebeiro; V. Kamakoti 001 (CoRR, 2019)

Sparsity-Aware Caches to Accelerate Deep Neural Networks. - Vinod Ganesan; Sanchari Sen; Pratyush Kumar; Neel Gala; Kamakoti Veezhinathan; Anand Raghunathan (DATE, 2020)

PERI: A Configurable Posit Enabled RISC-V Core. - Sugandha Tiwari; Neel Gala; Chester Rebeiro; V. Kamakoti 001 (ACM Trans. Archit. Code Optim., 2021)