A 0.3 V, 49 fJ/conv.-step VCO-based delta sigma modulator with self-compensated current reference for variation tolerance. - Neelakantan Narasimman; Tony T. Kim (ESSCIRC, 2016)

An ultra-low voltage, VCO-based ADC with digital background calibration. - Neelakantan Narasimman; Tony T. Kim (ISCAS, 2016)

A 1.2 V, 0.84 pJ/conv.-Step ultra-low power capacitance to digital converter for microphone based auscultation. - Neelakantan Narasimman; Dipankar Nag; Kevin Tshun Chuan Chai; Tony T. Kim (CICC, 2017)

An 86% efficiency Multi-Phase Buck Converter using Time-Domain Compensator and Adaptive Dead-Time Control for DVS Application. - Neelakantan Narasimman; Raju Salahuddin; Ravinder Pal Singh (IECON, 2020)

A 0.6-to-1.2 V Scaling Friendly Discrete-Time OTA-Free ΔΣ-ADC for IoT Applications. - Kyung-Chan An; Neelakantan Narasimman; Tony Tae-Hyoung Kim (ESSCIRC, 2021)

An Ultra-Low-Voltage VCO-Based ΔΣ Modulator Using Self-compensated Current Reference for Variation Tolerance. - Neelakantan Narasimman; Tony Tae-Hyoung Kim (Circuits Syst. Signal Process., 2021)

A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣ ADC Suitable for DVFS. - Kyung-Chan An; Neelakantan Narasimman; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A High-Resolution Discrete-Time Second-Order ΣΔ ADC with Improved Tolerance to KT/C Noise Using Low Oversampling Ratio. - Kyung-Chan An; Neelakantan Narasimman; Tony Tae-Hyoung Kim (Sensors, 2024)