An insensitive current mode universal biquad: multi-input multi-output. - Neeta Pandey; Sajal K. Paul; Asok Bhattacharyya (ISCAS (4), 2005)

A novel current controlled current mode universal filter: SITO approach. - Neeta Pandey; Sajal K. Paul; Asok Bhattacharyya; S. B. Jain (IEICE Electron. Express, 2005)

A new mixed mode biquad using reduced number of active and passive elements. - Neeta Pandey; Sajal K. Paul; Asok Bhattacharyya; S. B. Jain (IEICE Electron. Express, 2006)

SIMO Transadmittance Mode Active-C Universal Filter. - Neeta Pandey; Sajal K. Paul (Circuits Syst., 2010)

New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic. - Kirti Gupta; Ranjana Sridhar; Jaya Chaudhary; Neeta Pandey; Maneesha Gupta (J. Electr. Comput. Eng., 2011)

MO-CCCCTA-Based Floating Positive and Negative Inductors and Their Applications. - Neeta Pandey; Rishik Bazaz; Rahul Manocha (J. Electr. Comput. Eng., 2011)

Single CDTA-Based Current Mode All-Pass Filter and Its Applications. - Neeta Pandey; Sajal K. Paul (J. Electr. Comput. Eng., 2011)

Differential Difference Current Conveyor Transconductance Amplifier: A New Analog Building Block for Signal Processing. - Neeta Pandey; Sajal K. Paul (J. Electr. Comput. Eng., 2011)

Operational Transresistance Amplifier-Based Multiphase Sinusoidal Oscillators. - Rajeshwari Pandey; Neeta Pandey; Mayank Bothra; Sajal K. Paul (J. Electr. Comput. Eng., 2011)

New Topologies of Lossless Grounded Inductor Using OTRA. - Rajeshwari Pandey; Neeta Pandey; Sajal K. Paul; Aditya Singh; B. Sriram; Kaushalendra Trivedi (J. Electr. Comput. Eng., 2011)

An expandable current-mode ADC with power optimization technique. - Veepsa Bhatia; Neeta Pandey; Asok Bhattacharyya (RAIT, 2012)

Mixed Mode Universal filter. - Neeta Pandey; Sajal K. Paul (J. Circuits Syst. Comput., 2013)

Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells. - Kirti Gupta; Neeta Pandey; Maneesha Gupta (Microelectron. J., 2013)

Novel grounded inductance simulator using single OTRA. - Rajeshwari Pandey; Neeta Pandey; Sajal K. Paul; Ajay Singh; B. Sriram; Kaushlendra Trivedi (Int. J. Circuit Theory Appl., 2014)

An efficient triple-tail cell based PFSCL D latch. - Neeta Pandey; Kirti Gupta; Maneesha Gupta (Microelectron. J., 2014)

Approach for third order quadrature oscillator realisation. - Neeta Pandey; Rajeshwari Pandey (IET Circuits Devices Syst., 2015)

A Novel Ultra Low Power Current Comparator. - Veepsa Bhatia; Neeta Pandey (ICACDS, 2016)

A Novel Bulk Drain Connected 6T SRAM Cell. - Shobhit Kareer; Anchit Kumar; Kirti Gupta; Neeta Pandey (ICACDS, 2016)

Universal biquadratic filter using Operational Floating Current Conveyor (OFCC). - Divyesh Sachan; Deva Nand; Neeta Pandey (ICM, 2016)

Generalised operational floating current conveyor based instrumentation amplifier. - Neeta Pandey; Deva Nand; Rajeshwari Pandey (IET Circuits Devices Syst., 2016)

MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells. - Neeta Pandey; Kirti Gupta; Garima Bhatia; Bharat Choudhary (Microelectron. J., 2016)

New Proposal for MCML Based Three-Input Logic Implementation. - Neeta Pandey; Kirti Gupta; Bharat Choudhary (VLSI Design, 2016)

Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies. - Naman Saxena; Shruti Dutta; Neeta Pandey; Kirti Gupta (ICCSA (6), 2017)

New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies. - Neeta Pandey; Bharat Choudhary; Kirti Gupta; Ankit Mittal (J. Circuits Syst. Comput., 2017)

On Improving the Performance of Dynamic DCVSL Circuits. - Pratibha Bajpai; Neeta Pandey; Kirti Gupta; Shrey Bagga; Jeebananda Panda (J. Electr. Comput. Eng., 2017)

Modified Tang and Pun's Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs. - Veepsa Bhatia; Neeta Pandey (J. Electr. Comput. Eng., 2017)

A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist. - Shourya Gupta; Kirti Gupta; Neeta Pandey (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Design of an SCL logic based Current Comparator. - Veepsa Bhatia; Neeta Pandey; Sri Ranjani Prasanthi (MWSCAS, 2018)

MCML Dynamic Register Design. - Neeta Pandey; Kirti Gupta; Bharat Choudhary (MWSCAS, 2018)

OTRA Based Log and Antilog Amplifiers. - Rajeshwari Pandey; Neeta Pandey (MWSCAS, 2018)

Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System. - Preyesh Dalmia; Vikas; Abhinav Parashar; Akshi Tomar; Neeta Pandey (VLSID, 2018)

Pentavariate Vmin Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read. - Shourya Gupta; Kirti Gupta; Neeta Pandey (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Hardware/Software Co-Design of a High-Speed Othello Solver. - Pranav Gangwar; Satvik Maurya; Shubham Garg; Sakshi Goyal; Aditya S. Kumar; Preyesh Dalmia; Neeta Pandey (MWSCAS, 2019)

Novel Control Unit Design for a High-Speed SHA-3 Architecture. - Pranav Gangwar; Neeta Pandey; Rajeshwari Pandey (MWSCAS, 2019)

Programmable CCCII: reliability analysis and design methodology. - Manoj Kumar Tiwari; Neeta Pandey; Sajal K. Paul; Saiyid Mohammad Irshad Rizvi (IET Circuits Devices Syst., 2019)

New sinusoidal oscillator configurations using operational transresistance amplifier. - Gurumurthy Komanapalli; Rajeshwari Pandey; Neeta Pandey (Int. J. Circuit Theory Appl., 2019)

Realization of Resistorless and Electronically Tunable Inverse Filters Using VDTA. - Praveen Kumar; Neeta Pandey; Sajal K. Paul (J. Circuits Syst. Comput., 2019)

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS. - Shourya Gupta; Kirti Gupta; Benton H. Calhoun; Neeta Pandey (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Operational Transresistance Amplifier Based Wienbridge Oscillator and Its Harmonic Analysis. - Gurumurthy Komanapalli; Rajeshwari Pandey; Neeta Pandey (Wirel. Pers. Commun., 2019)

Model and Design of Improved Current Mode Logic Gates - Differential and Single-ended - Kirti Gupta; Neeta Pandey; Maneesha Gupta (Springer, 2020)

A new realization scheme for dynamic PFSCL style. - Ranjana Sivaram; Kirti Gupta; Neeta Pandey (Integr., 2020)

A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability. - Prakhar Sharma; Shourya Gupta; Kirti Gupta; Neeta Pandey (Microelectron. J., 2020)

A data-independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub-threshold region. - Monica Gupta; Kirti Gupta; Neeta Pandey (Int. J. Circuit Theory Appl., 2021)

A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region. - Monica Gupta; Kirti Gupta; Neeta Pandey (Int. J. Circuit Theory Appl., 2021)

Generalization of shadow filters in fractional domain. - Garima Varshney; Neeta Pandey; Rajeshwari Pandey (Int. J. Circuit Theory Appl., 2021)

Leakage reduction in dual mode logic through gated leakage transistors. - Neetika Yadav; Neeta Pandey; Deva Nand (Microprocess. Microsystems, 2021)

A novel design for voltage inverting metamutator and its applications. - R. Arundeepakvel; Jatin; Parth Khatter; Neeta Pandey; Shahram Minaei (Microelectron. J., 2021)

Clock Aligned Input Adiabatic Logic. - Aditya S. Kumar; Sagar Jain; Neeta Pandey (Microelectron. J., 2021)

Unified floating immittance emulator based on CCTA. - Navnit Kumar; Manjeet Kumar; Neeta Pandey (Microelectron. J., 2021)

Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm. - Monica Gupta; Kirti Gupta; Neeta Pandey (Microprocess. Microsystems, 2021)

OTA Based Fractional-Order Oscillator With Controlled Phase Difference. - Garima Varshney; Neeta Pandey; Rajeshwari Pandey (ISCAS, 2022)

A novel design of a 1 GHz phase locked loop with improved lock time for fast frequency acquisition. - Monika Bhardwaj; Sujata Pandey; Neeta Pandey (Int. J. Comput. Aided Eng. Technol., 2022)

Novel Pehlivan-Uyarŏglu Chaotic System Variants and their CFOA Based Realization. - Kriti Suneja; Neeta Pandey; Rajeshwari Pandey (J. Circuits Syst. Comput., 2022)

A novel read decoupled 8T1M nvSRAM cell for near threshold operation. - Damyanti Singh; Kirti Gupta; Neeta Pandey (Microelectron. J., 2022)

On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates. - Ranjana Sivaram; Kirti Gupta; Neeta Pandey (Microprocess. Microsystems, 2022)

Refining RNMC compensation for Three Stage Amplifier using DTMOS Transistor and FFVF. - Om Krishna Gupta; Neeta Pandey; Maneesha Gupta (ICCCNT, 2023)

Real Time Control System for Metro Railways Using PLC & SCADA. - Ishu Tomar; Indu Sreedevi; Neeta Pandey (Intell. Autom. Soft Comput., 2023)

Electronically tunable positive and negative fractional order inductor circuit using single topology. - Navnit Kumar; Manjeet Kumar; Neeta Pandey (Integr., 2023)

CCTA based four different pairs of mutually coupled circuit using single topology. - Navnit Kumar; Manjeet Kumar; Neeta Pandey (Integr., 2023)

Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell. - Damyanti Singh; Neeta Pandey; Kirti Gupta (Microelectron. J., 2023)

PLC and SCADA based Real Time Monitoring and Train Control System for the Metro Railways Infrastructure. - Ishu Tomar; Indu Sreedevi; Neeta Pandey (Wirel. Pers. Commun., 2023)

LDML: A Proposal to Reduce Leakage Power in DML Circuits. - Neetika Yadav; Neeta Pandey; Deva Nand (Wirel. Pers. Commun., 2023)

Memristor-Based Architectures for PFSCL Circuit Realizations. - Shikha 001; Neeta Pandey; Kirti Gupta (Circuits Syst. Signal Process., 2023)

Modified Dual Mode Transmission Gate Diffusion Input Logic for Improving Energy Efficiency. - Neetika Yadav; Neeta Pandey; Deva Nand (J. Circuits Syst. Comput., 2023)

Modeling of Dual- Metal Junctionless Accumulation-Mode cylindrical surrounding gate (DM-JAM-CSG) MOSFET for cryogenic temperature applications. - Sumedha Gupta; Neeta Pandey; R. S. Gupta (Microelectron. J., 2023)

A Novel Chaotic System with Exponential Nonlinearity and its Adaptive Self-Synchronization: From Numerical Simulations to Circuit Implementation. - Kriti Suneja; Neeta Pandey; Rajeshwari Pandey (J. Circuits Syst. Comput., 2023)

A low power Schmitt-trigger driven 10T SRAM Cell for high speed applications. - Lokesh Soni; Neeta Pandey (Integr., 2024)

A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell. - Lokesh Soni; Neeta Pandey (ACM Trans. Design Autom. Electr. Syst., 2024)

High-performance radiation hardened latch using Schmitt trigger. - Niraj Kumar; Chaudhary Indra Kumar; Neeta Pandey (Integr., 2025)

Resistorless Realization of Three-Port Circulator using Operational Transconductance Amplifiers. - Priyanka Gupta 001; Neeta Pandey; Rajeshwari Pandey (J. Circuits Syst. Comput., 2025)

Frequency Compensation of Three-Stage Amplifier with Self-Cascode Structure and DTMOS Transistor with Active LHP Zero Circuit. - Om Krishna Gupta; Neeta Pandey; Maneesha Gupta (J. Circuits Syst. Comput., 2025)

Single Topology-Based Reconfigurable Positive and Negative Immittance Circuit and its Application as Multifunction Filter and Quadrature Oscillator. - Navnit Kumar; Manjeet Kumar; Neeta Pandey (J. Circuits Syst. Comput., 2025)

A robust, low power and high speed radiation hardened 12T SRAM cell for space applications. - Lokesh Soni; Neeta Pandey (Microelectron. J., 2025)

Second generation current conveyor based capacitorless floating memristor emulator. - Navnit Kumar; Manjeet Kumar; Neeta Pandey; Shahram Minaei (Int. J. Circuit Theory Appl., 2025)