Leakage reduction in dual mode logic through gated leakage transistors. - Neetika Yadav; Neeta Pandey; Deva Nand (Microprocess. Microsystems, 2021)

LDML: A Proposal to Reduce Leakage Power in DML Circuits. - Neetika Yadav; Neeta Pandey; Deva Nand (Wirel. Pers. Commun., 2023)

Modified Dual Mode Transmission Gate Diffusion Input Logic for Improving Energy Efficiency. - Neetika Yadav; Neeta Pandey; Deva Nand (J. Circuits Syst. Comput., 2023)