SIxD: A Configurable Application-Specific SISD/SIMD Microprocessor Soft-Core. - Nehir Sönmez; Arda Yurdakul (SoC, 2006)

unreadTVar: Extending Haskell Software Transactional Memory for Performance. - Nehir Sönmez; Cristian Perfumo; Srdjan Stipic; Adrián Cristal; Osman S. Unsal; Mateo Valero (Trends in Functional Programming, 2007)

The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. - Cristian Perfumo; Nehir Sönmez; Srdjan Stipic; Osman S. Unsal; Adrián Cristal; Tim Harris 001; Mateo Valero (Conf. Computing Frontiers, 2008)

Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. - Nehir Sönmez; Tim Harris 001; Adrián Cristal; Osman S. Unsal; Mateo Valero (IPDPS, 2009)

From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype. - Nehir Sönmez; Oriol Arcas; Gokhan Sayilar; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Satnam Singh; Mateo Valero (ARC, 2011)

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. - Nehir Sönmez; Oriol Arcas; Otto Pflucker; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Satnam Singh; Mateo Valero (FCCM, 2011)

A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory. - Oriol Arcas; Philipp Kirchhofer; Nehir Sönmez; Martin Schindewolf; Osman S. Unsal; Wolfgang Karl; Adrián Cristal (FCCM, 2012)

Resource-bounded multicore emulation using Beefarm. - Oriol Arcas; Nehir Sönmez; Gokhan Sayilar; Satnam Singh; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (Microprocess. Microsystems, 2012)

A multicore emulator with a profiling Infrastructure for transactional memory on FPGA. - Nehir Sönmez (2012)

An empirical evaluation of High-Level Synthesis languages and tools for database acceleration. - Oriol Arcas-Abella; Geoffrey Ndu; Nehir Sönmez; Mohsen Ghasempour; Adrià Armejach; Javier Navaridas; Wei Song 002; John Mawer; Adrián Cristal; Mikel Luján (FPL, 2014)

PAMS: Pattern Aware Memory System for embedded systems. - Tassadaq Hussain; Nehir Sönmez; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero; Shakaib A. Gursal (ReConFig, 2014)

HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA. - Behzad Salami 001; Oriol Arcas-Abella; Nehir Sönmez (FCCM, 2015)

Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology (Abstract Only). - Gorker Alp Malazgirt; Nehir Sönmez; Arda Yurdakul; Osman S. Unsal; Adrián Cristal (FPGA, 2015)

High Level Synthesis Based Hardware Accelerator Design for Processing SQL Queries. - Gorker Alp Malazgirt; Nehir Sönmez; Arda Yurdakul; Adrián Cristal; Osman S. Unsal (FPGAworld, 2015)

Bluespec SystemVerilog. - Oriol Arcas-Abella; Nehir Sönmez (FPGAs for Software Programmers, 2016)

Big Data and HPC Acceleration with Vivado HLS. - Moritz Schmid; Christian Schmitt 003; Frank Hannig; Gorker Alp Malazgirt; Nehir Sönmez; Arda Yurdakul; Adrián Cristal (FPGAs for Software Programmers, 2016)

Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique. - Behzad Salami 001; Oriol Arcas-Abella; Nehir Sönmez; Osman S. Unsal; Adrián Cristal Kestelman (CARLA, 2016)

Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory. - Oriol Arcas-Abella; Adrià Armejach; Timothy Hayes 001; Gorker Alp Malazgirt; Oscar Palomar; Behzad Salami 001; Nehir Sönmez (Comput. Sci. Eng., 2016)

AxleDB: A novel programmable query processing platform on FPGA. - Behzad Salami 001; Gorker Alp Malazgirt; Oriol Arcas-Abella; Arda Yurdakul; Nehir Sönmez (Microprocess. Microsystems, 2017)

Evaluation of a Rack-Scale Disaggregated Memory Prototype for Cloud Data Centers. - Josue V. Quiroga; Martí Torrents; Nehir Sönmez; Dimitris Theodoropoulos; Ferad Zyulkyarov; Mario Nemirovsky (RSP, 2019)

An Academic RISC-V Silicon Implementation Based on Open-Source Components. - Jaume Abella 001; Calvin Bulla; Guillem Cabo; Francisco J. Cazorla; Adrián Cristal; Max Doblas; Roger Figueras; Alberto González 004; Carles Hernández 001; César Hernández; Víctor Jiménez; Leonidas Kosmidis; et al. (DCIS, 2020)

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. - Guillem Cabo; Gerard Candón; Xavier Carril; Max Doblas; Marc Domínguez; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2022)

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. - Max Doblas; Gerard Candón; Xavier Carril; Marc Domínguez; Enric Erra; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2023)

Functional Verification of a RISC-V Vector Accelerator. - Víctor Jiménez; Mario Rodríguez; Marc Domínguez; Josep Sans; Ivan Diaz; Luca Valente; Vito Luca Guglielmi; Josue V. Quiroga; R. Ignacio Genovese; Nehir Sönmez; Oscar Palomar; Miquel Moretó (IEEE Des. Test, 2023)