An Effective BIST Architecture for Fast Multiplier Cores. - Antonis M. Paschalis; Nektarios Kranitis; Mihalis Psarakis; Dimitris Gizopoulos; Yervant Zorian (DATE, 1999)

Effective Low Power BIST for Datapaths. - Dimitris Gizopoulos; Nektarios Kranitis; Mihalis Psarakis; Antonis M. Paschalis; Yervant Zorian (DATE, 2000)

Deterministic Built-In Self -Test for Shifters, Adders and ALUs in Datapaths. - Mihalis Psarakis; Nektarios Kranitis; Dimitris Gizopoulos; Antonis M. Paschalis; Yervant Zorian (LATW, 2000)

Low Power/Energy BIST Scheme for Datapaths. - Dimitris Gizopoulos; Nektarios Kranitis; Mihalis Psarakis; Antonis M. Paschalis; Yervant Zorian (VTS, 2000)

Power-/Energy Efficient BIST Schemes for Processor Data Paths. - Nektarios Kranitis; Dimitris Gizopoulos; Antonis M. Paschalis; Mihalis Psarakis; Yervant Zorian (IEEE Des. Test Comput., 2000)

Deterministic software-based self-testing of embedded processor cores. - Antonis M. Paschalis; Dimitris Gizopoulos; Nektarios Kranitis; Mihalis Psarakis; Yervant Zorian (DATE, 2001)

Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. - Mihalis Psarakis; Antonis M. Paschalis; Nektarios Kranitis; Dimitris Gizopoulos; Yervant Zorian (VTS, 2001)

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. - Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos; Mihalis Psarakis; Yervant Zorian (J. Electron. Test., 2001)

Effective Software Self-Test Methodology for Processor Cores. - Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos; Yervant Zorian (DATE, 2002)

Low-Cost Software-Based Self-Testing of RISC Processor Cores. - Nektarios Kranitis; George Xenoulis; Dimitris Gizopoulos; Antonis M. Paschalis; Yervant Zorian (DATE, 2003)

Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores. - George Xenoulis; Dimitris Gizopoulos; Nektarios Kranitis; Antonis M. Paschalis (IOLTS, 2003)

Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores. - Nektarios Kranitis; George Xenoulis; Antonis M. Paschalis; Dimitris Gizopoulos; Yervant Zorian (ITC, 2003)

Instruction-Based Self-Testing of Processor Cores. - Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos; Yervant Zorian (J. Electron. Test., 2003)

Software-Based Self-Testing of Embedded Processors. - Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos; George Xenoulis (IEEE Trans. Computers, 2005)

A concurrent built-in self-test architecture based on a self-testing RAM. - Ioannis Voyiatzis; Antonis M. Paschalis; Dimitris Gizopoulos; Nektarios Kranitis; Constantin Halatsis (IEEE Trans. Reliab., 2005)

Αποδοτικές τεχνικές ενσωματωμένης αυτοδοκιμής για επεξεργαστές τεχνολογίας CMOS VLSI βασισμένες στην αρχιτεκτονική του συνόλου εντολών - Nektarios Kranitis (2005)

Optimal periodic testing of intermittent faults in embedded pipelined processor applications. - Nektarios Kranitis; Andreas Merentitis; Nikolaos Laoutaris; George Theodorou; Antonis M. Paschalis; Dimitris Gizopoulos; Constantin Halatsis (DATE, 2006)

A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs. - P. Kenterlis; Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos; Mihalis Psarakis (IOLTS, 2006)

Selecting Power-Optimal SBST Routines for On-Line Processor Testing. - Andreas Merentitis; Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos (ETS, 2007)

Directed Random SBST Generation for On-Line Testing of Pipelined Processors. - Andreas Merentitis; George Theodorou; Mihalis Giorgaras; Nektarios Kranitis (IOLTS, 2008)

Low Energy On-Line SBST of Embedded Processors. - Andreas Merentitis; Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos (ITC, 2008)

Hybrid-SBST Methodology for Efficient Testing of Processor Cores. - Nektarios Kranitis; Andreas Merentitis; George Theodorou; Antonis M. Paschalis; Dimitris Gizopoulos (IEEE Des. Test Comput., 2008)

Energy optimal on-line Self-Test of microprocessors in WSN nodes. - Andreas Merentitis; Antonis M. Paschalis; Dimitris Gizopoulos; Nektarios Kranitis (ICCD, 2010)

SBST for on-line detection of hard faults in multiprocessor applications under energy constraints. - Andreas Merentitis; Dionisis Margaris; Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos (IOLTS, 2010)

A software-based self-test methodology for in-system testing of processor cache tag arrays. - George Theodorou; Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos (IOLTS, 2010)

A Software-Based Self-Test methodology for on-line testing of processor caches. - George Theodorou; Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos (ITC, 2011)

A Software-Based Self-Test methodology for on-line testing of data TLBs. - George Theodorou; Serafeim Chatzopoulos; Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos (ETS, 2012)

Low Energy Online Self-Test of Embedded Processors in Dependable WSN Nodes. - Andreas Merentitis; Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos (IEEE Trans. Dependable Secur. Comput., 2012)

Software-Based Self Test Methodology for On-Line Testing of L1 Caches in Multithreaded Multicore Architectures. - Giorgos Theodorou; Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Dependable reconfigurable space systems: Challenges, new trends and case studies. - Antonis M. Paschalis; Harald Michalik; Nektarios Kranitis; Celia López-Ongil; Pedro Reviriego Vasallo (IOLTS, 2014)

Power-aware optimization of software-based self-test for L1 caches in microprocessors. - George Theodorou; Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos (IOLTS, 2014)

Software-Based Self-Test for Small Caches in Microprocessors. - Georgios Theodorou; Nektarios Kranitis; Antonis M. Paschalis; Dimitris Gizopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A single chip dependable and adaptable payload Data Processing Unit. - Nektarios Kranitis; Antonis Tsigkanos; George Theodorou; Ioannis Sideris; Antonis M. Paschalis (IOLTS, 2015)

An efficient LDPC encoder architecture for space applications. - Dimitris Theodoropoulos; Nektarios Kranitis; Antonis M. Paschalis (IOLTS, 2016)

Analyzing the Resilience to SEUs of an Image Data Compression Core in a COTS SRAM FPGA. - Ioannis Tsounis; Antonis Tsigkanos; Vasileios Vlagkoulis; Mihalis Psarakis; Nektarios Kranitis; Antonis M. Paschalis (AHS, 2019)

Efficient LDPC Encoder Designs for Magnetic Recording Media. - Dimitris Theodoropoulos; Nektarios Kranitis; Antonis Tsigkanos; Antonis M. Paschalis (DFT, 2020)

Efficient Architectures for Multigigabit CCSDS LDPC Encoders. - Dimitris Theodoropoulos; Nektarios Kranitis; Antonis Tsigkanos; Antonis M. Paschalis (IEEE Trans. Very Large Scale Integr. Syst., 2020)

High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1. - Antonis Tsigkanos; Nektarios Kranitis; Dimitris Theodoropoulos; Antonis M. Paschalis (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 3.3 Gbps CCSDS 123.0-B-1 Multispectral & Hyperspectral Image Compression Hardware Accelerator on a Space-Grade SRAM FPGA. - Antonis Tsigkanos; Nektarios Kranitis; George Theodorou; Antonis M. Paschalis (IEEE Trans. Emerg. Top. Comput., 2021)

High-Performance Hardware Accelerators for Next Generation On-Board Data Processing. - Antonis M. Paschalis; Panagiotis Chatziantoniou; Dimitris Theodoropoulos; Antonis Tsigkanos; Nektarios Kranitis (VLSI-SoC, 2022)

An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology. - Panagiotis Chatziantoniou; Antonis Tsigkanos; Dimitris Theodoropoulos; Nektarios Kranitis; Antonis M. Paschalis (IEEE Trans. Aerosp. Electron. Syst., 2022)

Efficient Hardware Architectures and Implementations of Packet-Level Erasure Coding Schemes for High Data Rate Reliable Satellite Communications. - Dimitris Theodoropoulos; Nektarios Kranitis; Antonis M. Paschalis; Elias Machairas; Antonios Paschalis (IEEE Trans. Aerosp. Electron. Syst., 2022)

A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance. - Panagiotis Chatziantoniou; Antonis Tsigkanos; Dimitris Theodoropoulos; Nektarios Kranitis; Antonis M. Paschalis (IEEE Trans. Very Large Scale Integr. Syst., 2024)