A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS. - Nereo Markulic; Kuba Raczkowski; Piet Wambacq; Jan Craninckx (ESSCIRC, 2014)

A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter. - Kuba Raczkowski; Nereo Markulic; Benjamin P. Hershberg; Jan Craninckx (IEEE J. Solid State Circuits, 2015)

9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. - Nereo Markulic; Kuba Raczkowski; Ewout Martens; Pedro Emiliano Paro Filho; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (ISSCC, 2016)

A Fractional-n subsampling PLL based on a digital-to-time converter. - Nereo Markulic; Kuba Raczkowski; Piet Wambacq; Jan Craninckx (MIPRO, 2016)

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. - Nereo Markulic; Kuba Raczkowski; Ewout Martens; Pedro Emiliano Paro Filho; Benjamin P. Hershberg; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2016)

24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications. - Yuming He; Yao-Hong Liu; Takashi Kuramochi; Johan H. C. van den Heuvel; Benjamin Busze; Nereo Markulic; Christian Bachmann; Kathleen Philips (ISSCC, 2017)

A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. - Nereo Markulic; Pratap Renukaswarny; Ewout Martens; Barend van Liempd; Piet Wambacq; Jan Craninckx (VLSI Circuits, 2018)

A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. - Benjamin P. Hershberg; Davide Dermit; Barend van Liempd; Ewout Martens; Nereo Markulic; Jorge Lagos 001; Jan Craninckx (ISSCC, 2019)

A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. - Benjamin P. Hershberg; Barend van Liempd; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (ISSCC, 2019)

A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error. - Qixian Shi; Keigo Bunsen; Nereo Markulic; Jan Craninckx (ISSCC, 2019)

A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. - Nereo Markulic; Pratap Tumkur Renukaswamy; Ewout Martens; Barend van Liempd; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2019)

A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth. - Qixian Shi; Keigo Bunsen; Nereo Markulic; Jan Craninckx (IEEE J. Solid State Circuits, 2019)

17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. - Pratap Tumkur Renukaswamy; Nereo Markulic; Sehoon Park; Anirudh Kankuppe; Qixian Shi; Piet Wambacq; Jan Craninckx (ISSCC, 2020)

A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. - Benjamin P. Hershberg; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (VLSI Circuits, 2020)

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. - Pratap Tumkur Renukaswamy; Nereo Markulic; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2020)

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. - Pratap Tumkur Renukaswamy; Nereo Markulic; Piet Wambacq; Jan Craninckx (ISCAS, 2021)

A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. - Jorge Lagos 001; Nereo Markulic; Benjamin P. Hershberg; Davide Dermit; Mithlesh Shrivas; Ewout Martens; Jan Craninckx (VLSI Circuits, 2021)

An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC. - Lai Wei; Zihao Zheng; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Yan Zhu 001; Chi-Hang Chan; Jan Craninckx; Rui Paulo Martins (VLSI Circuits, 2021)

A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. - Benjamin P. Hershberg; Davide Dermit; Barend van Liempd; Ewout Martens; Nereo Markulic; Jorge Lagos 001; Jan Craninckx (IEEE J. Solid State Circuits, 2021)

A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. - Benjamin P. Hershberg; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (IEEE J. Solid State Circuits, 2021)

Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. - Benjamin P. Hershberg; Barend van Liempd; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Davide Dermit; Jan Craninckx (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. - Jorge Lagos 001; Nereo Markulic; Benjamin P. Hershberg; Davide Dermit; Mithlesh Shrivas; Ewout Martens; Jan Craninckx (IEEE J. Solid State Circuits, 2022)

Calibration Techniques for Optimizing Performance of High-Speed ADCs. - Ewout Martens; Nereo Markulic; Jorge Luis Lagos-Benites; Jan Craninckx (CICC, 2023)

A 16GHz, $41 text{kHz}_{ text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL. - Pratap Tumkur Renukaswamy; Kristof Vaesen; Nereo Markulic; Veerle Derudder; Dae-Woong Park; Piet Wambacq; Jan Craninckx (ISSCC, 2023)

A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. - Lai Wei; Zihao Zheng; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Rui Paulo Martins; Yan Zhu 001; Jan Craninckx; Chi-Hang Chan (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. - Ewout Martens; Adam Cooman; Pratap Tumkur Renukaswamy; Shun Nagata; Sehoon Park; Jorge-Luis Lagos 001; Nereo Markulic; Jan Craninckx (ISSCC, 2024)

A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS. - Jorge Lagos 001; Pratap Tumkur Renukaswamy; Nereo Markulic; Ewout Martens; Jan Craninckx (VLSI Technology and Circuits, 2024)

A 10GS/s Hierarchical Time-Interleaved ADC for RF-Sampling Applications. - Nereo Markulic; Johan Nguyen; Jorge Luis Lagos-Benites; Ewout Martens; Jan Craninckx (VLSI Technology and Circuits, 2024)

A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL. - Pratap Tumkur Renukaswamy; Kristof Vaesen; Nereo Markulic; Jan Craninckx (IEEE J. Solid State Circuits, 2024)