3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs. - Lingjun Zhu; Nesara Eranna Bethur; Yi-Chen Lu; Youngsang Cho; Yunhyeok Im; Sung Kyu Lim (ISLPED, 2022)

GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. - Nesara Eranna Bethur; Pruek Vanna-Iampikul; Odysseas Zografos; Lingjun Zhu; Giuliano Sisto; Dragomir Milojevic; Alberto García Ortiz; Geert Hellings; Julien Ryckaert; Francky Catthoor; Sung Kyu Lim (DAC, 2024)

Back-side Design Methodology for Power Delivery Network and Clock Routing. - Pruek Vanna-Iampikul; Hang Yang; Jungyoun Kwak; Joyce X. Hu; Amaan Rahman; Nesara Eranna Bethur; Callie Hao; Shimeng Yu; Sung Kyu Lim (VLSI Technology and Circuits, 2024)

Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. - Nesara Eranna Bethur; Anthony Agnesina; Moritz Brunion; Alberto García Ortiz; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Matheus A. Cavalcante; Samuel Riedel; Luca Benini; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)