Reducing the Branch Penalty by Rearranging Instructions in Double-Width Memory. - Manolis Katevenis; Nestoras Tzartzanis (ASPLOS, 1991)

Low-power digital systems based on adiabatic-switching principles. - William C. Athas; Lars J. Svensson; Jefferey G. Koller; Nestoras Tzartzanis; E. Ying-Chin Chou (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Energy recovery for low-power CMOS. - William C. Athas; Nestoras Tzartzanis (ARVLSI, 1995)

Design and analysis of a low-power energy-recovery adder. - Nestoras Tzartzanis; William C. Athas (Great Lakes Symposium on VLSI, 1995)

Energy recovery for the design of high-speed, low-power static RAMs. - Nestoras Tzartzanis; William C. Athas (ISLPED, 1996)

AC-1: a clock-powered microprocessor. - William C. Athas; Nestoras Tzartzanis; Lars J. Svensson; Lena Peterson; Huimin Li; Xing Yu Jiang; Peiqing Wang; Weichuan Liu (ISLPED, 1997)

A low-power microprocessor based on resonant energy. - William C. Athas; Nestoras Tzartzanis; Lars J. Svensson; Lena Peterson (IEEE J. Solid State Circuits, 1997)

Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing. - Nestoras Tzartzanis; William C. Athas (ARVLSI, 1999)

Retractile clock-powered logic. - Nestoras Tzartzanis; William C. Athas (ISLPED, 1999)

The design and implementation of a low-power clock-powered microprocessor. - William C. Athas; Nestoras Tzartzanis; Weihua Mao; Lena Peterson; Rajat Lal; Kisup Chong; Joong-Seok Moon; Lars J. Svensson; Michael Bolotski (IEEE J. Solid State Circuits, 2000)

A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File. - Nestoras Tzartzanis; William W. Walker (ICCD, 2003)

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. - Yusuke Okaniwa; Hirotaka Tamura; Masaya Kibune; Daisuke Yamazaki; Tsz-Shing Cheung; Junji Ogawa; Nestoras Tzartzanis; William W. Walker; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

Differential current-mode sensing for efficient on-chip global signaling. - Nestoras Tzartzanis; William W. Walker (IEEE J. Solid State Circuits, 2005)

A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing. - Hisashige Ando; Nestoras Tzartzanis; William W. Walker (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A Reversible Poly-Phase Distributed VCO. - Nestoras Tzartzanis; William W. Walker (ISSCC, 2006)

A 40-to-44Gb/s 3? Oversampling CMOS CDR/1: 16 DEMUX. - Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker (ISSCC, 2007)

A Leakage Current Replica Keeper for Dynamic Circuits. - Yolin Lih; Nestoras Tzartzanis; William W. Walker (IEEE J. Solid State Circuits, 2007)

A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. - Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker (IEEE J. Solid State Circuits, 2007)

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (ISSCC, 2009)

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (IEEE J. Solid State Circuits, 2009)

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. - Nikola Nedovic; Anders Kristensson; Samir Parikh; Subodh M. Reddy; Scott McLeod; Nestoras Tzartzanis; Kouichi Kanda; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Satoshi Ide; et al. (IEEE J. Solid State Circuits, 2010)