Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion. - Kok Lim Chan; Nevena Rakuljic; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Tree-Structured DEM DACs with Arbitrary Numbers of Levels. - Nevena Rakuljic; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction. - Nevena Rakuljic; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology. - Siddharth Devarajan; Larry Singer; Dan Kelly; Steve Kosic; Tao Pan; José B. Silva; Janet Brunsilius; Daniel Rey-Losada; Frank Murden; Carroll Speir; Jeff Bray; Eric Otte; et al. (ISSCC, 2017)

A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology. - Siddharth Devarajan; Larry Singer; Dan Kelly; Tao Pan; José B. Silva; Janet Brunsilius; Daniel Rey-Losada; Frank Murden; Carroll Speir; Jeff Bray; Eric Otte; Nevena Rakuljic; et al. (IEEE J. Solid State Circuits, 2017)

In-situ nonlinear calibration of a RF signal chain. - Nevena Rakuljic; Carroll Speir; Eric Otte; Jeff Bray; Corey Petersen; Gabriele Manganaro (ISCAS, 2018)

24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET. - Junhua Shen; Wei-Hung Chen; Efram Burlingame; Stephen Weinreich; Michael Elliott; Stuart McCracken; Jack Kenney; Janet Brunsilius; Anil Korkmaz; Enrique Alvarez-Fontecilla; Nevena Rakuljic; Ushma Mehta; et al. (ISSCC, 2025)