Boolean constrained encoding: a new formulation and a case study. - Ney Laert Vilar Calazans (ICCAD, 1994)

Using the CAN Protocol and Reconfigurable Computing Technology for Web-Based Smart House Auto. - Fernando Moraes 001; Alexandre M. Amory; Ney Calazans; Eduardo Bezerra 001; Juracy Petrini (SBCCI, 2001)

Projeto para Prototipação de um IP Soft Core MAC Ethernet. - Ney Laert Vilar Calazans; Fernando Gehm Moraes; Delfim Luiz Torok; Andrey V. Andreoli (RITA, 2001)

Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses. - Ney Laert Vilar Calazans; Fernando Gehm Moraes (IEEE Trans. Educ., 2001)

Prototyping of embedded digital systems from SDL language: a case study. - César A. M. Marcon; Fabiano Hessel; Alexandre M. Amory; Luis H. L. Ries; Fernando Gehm Moraes; Ney Laert Vilar Calazans (HLDVT, 2002)

A Heterogeneous and Distributed Co-Simulation Environment. - Alexandre M. Amory; Fernando Moraes 001; Leandro A. Oliveira; Ney Calazans; Fabiano Hessel (SBCCI, 2002)

Requirements, Primitives and Models for Systems Specification. - César Augusto Missio Marcon; Ney Laert Vilar Calazans; Fernando Gehm Moraes (SBCCI, 2002)

Core Communication Interface for FPGAs. - José Carlos S. Palma; Aline Vieira de Mello; Leandro Möller; Fernando Moraes 001; Ney Calazans (SBCCI, 2002)

Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. - Fernando Gehm Moraes; Daniel Mesquita; José Carlos S. Palma; Leandro Möller; Ney Laert Vilar Calazans (DATE, 2003)

Remote and Partial Reconfiguration of FPGAs: Tools and Trends. - Daniel Mesquita; Fernando Gehm Moraes; José Palma 002; Leandro Möller; Ney Laert Vilar Calazans (IPDPS, 2003)

From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. - Ney Laert Vilar Calazans; Edson I. Moreno; Fabiano Hessel; Vitor M. da Rosa; Fernando Moraes 001; Everton Carara (SBCCI, 2003)

A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. - Fernando Gehm Moraes; Aline Mello 001; Leandro Möller; Luciano Ost; Ney Laert Vilar Calazans (VLSI-SOC, 2003)

MultiNoC: A Multiprocessing System Enabled by a Network on Chip. - Aline Mello 001; Leandro Möller; Ney Calazans; Fernando Gehm Moraes (DATE, 2004)

FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. - Leandro Möller; Ney Laert Vilar Calazans; Fernando Gehm Moraes; Eduardo Wenzel Brião; Ewerson Carvalho; Daniel Camozzato (FPL, 2004)

PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems. - Ewerson Carvalho; Ney Calazans; Eduardo Wenzel Brião; Fernando Moraes 001 (SBCCI, 2004)

HERMES: an infrastructure for low area overhead packet-switching networks on chip. - Fernando Gehm Moraes; Ney Calazans; Aline Mello 001; Leandro Möller; Luciano Ost (Integr., 2004)

MAIA: a framework for networks on chip generation and verification. - Luciano Ost; Aline Mello 001; José Palma 002; Fernando Gehm Moraes; Ney Calazans (ASP-DAC, 2005)

Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. - César A. M. Marcon; Ney Laert Vilar Calazans; Fernando Gehm Moraes; Altamiro Amadeu Susin; Igor M. Reis; Fabiano Hessel (DATE, 2005)

Energy and latency evaluation of NoC topologies. - Márcio Eduardo Kreutz; César A. M. Marcon; Luigi Carro; Altamiro Amadeu Susin; Ney Laert Vilar Calazans (ISCAS (6), 2005)

Models for Embedded Application Mapping onto NoCs: Timing Analysis. - César A. M. Marcon; Márcio Eduardo Kreutz; Altamiro Amadeu Susin; Ney Laert Vilar Calazans (IEEE International Workshop on Rapid System Prototyping, 2005)

Virtual channels in networks on chip: implementation and evaluation on hermes NoC. - Aline Mello 001; Leonel Tedesco; Ney Calazans; Fernando Moraes 001 (SBCCI, 2005)

Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. - José Carlos S. Palma; César A. M. Marcon; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Ricardo A. L. Reis; Altamiro Amadeu Susin (SBCCI, 2005)

Traffic generation and performance evaluation for mesh-based NoCs. - Leonel Tedesco; Aline Mello 001; Diego Garibotti; Ney Calazans; Fernando Moraes 001 (SBCCI, 2005)

Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. - César A. M. Marcon; José Carlos S. Palma; Ney Laert Vilar Calazans; Fernando Gehm Moraes; Altamiro Amadeu Susin; Ricardo Augusto da Luz Reis (VLSI-SoC, 2005)

Reconfigurable Systems Enabled by a Network-on-Chip. - Leandro Möller; Ismael Grehs; Ney Calazans; Fernando Moraes 001 (FPL, 2006)

Evaluation of current QoS Mechanisms in Networks on Chip. - Aline Mello 001; Leonel Tedesco; Ney Calazans; Fernando Moraes 001 (SoC, 2006)

Infrastructure for dynamic reconfigurable systems: choices and trade-offs. - Leandro Möller; Rafael Soares; Ewerson Carvalho; Ismael Grehs; Ney Calazans; Fernando Moraes 001 (SBCCI, 2006)

Application driven traffic modeling for NoCs. - Leonel Tedesco; Aline Mello 001; Leonardo Giacomet; Ney Calazans; Fernando Gehm Moraes (SBCCI, 2006)

SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. - Julian J. H. Pontes; Rafael Soares; Ewerson Carvalho; Fernando Moraes 001; Ney Calazans (ICCD, 2007)

Evaluation of Algorithms for Low Energy Mapping onto NoCs. - César A. M. Marcon; Edson I. Moreno; Ney Laert Vilar Calazans; Fernando Gehm Moraes (ISCAS, 2007)

MOTIM - A Scalable Architecture for Ethernet Switches. - Erico Bastos; Everton Carara; Daniel V. Pigatto; Ney Laert Vilar Calazans; Fernando Moraes 001 (ISVLSI, 2007)

Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. - Ewerson Carvalho; Ney Laert Vilar Calazans; Fernando Gehm Moraes (ISVLSI, 2007)

A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. - Leandro Möller; Ismael Grehs; Ewerson Carvalho; Rafael Soares; Ney Calazans; Fernando Moraes 001 (ReCoSoC, 2007)

SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems. - Luis Carlos Caruso; Guilherme Montez Guindani; Hugo Schmitt; Ney Calazans; Fernando Moraes 001 (IEEE International Workshop on Rapid System Prototyping, 2007)

Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs. - Ewerson Carvalho; Ney Calazans; Fernando Moraes 001 (IEEE International Workshop on Rapid System Prototyping, 2007)

Router architecture for high-performance NoCs. - Everton Carara; Fernando Moraes 001; Ney Calazans (SBCCI, 2007)

Buffer sizing for QoS flows in wormhole packet switching NoCs. - Leonel Tedesco; Fernando Moraes 001; Ney Calazans (SBCCI, 2007)

Rate-based scheduling policy for QoS flows in networks on chip. - Aline Mello 001; Ney Laert Vilar Calazans (VLSI-SoC, 2007)

QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques. - Aline Mello 001; Ney Calazans; Fernando Moraes 001 (VLSI-SoC (Selected Papers), 2007)

NoC Power Estimation at the RTL Abstraction Level. - Guilherme Montez Guindani; Cezar Reinbrecht; Thiago Raupp da Rosa; Ney Calazans; Fernando Gehm Moraes (ISVLSI, 2008)

Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. - Julian J. H. Pontes; Matheus T. Moreira; Rafael Soares; Ney Laert Vilar Calazans (ISVLSI, 2008)

Triple Rail Logic Robustness against DPA. - Victor Lomné; Thomas Ordas; Philippe Maurine; Lionel Torres; Michel Robert; Rafael Soares; Ney Calazans (ReConFig, 2008)

Integrating Abstract NoC Models within MPSoC Design. - Edson Ifarraguirre Moreno; Katalin Maria Popovici; Ney Laert Vilar Calazans; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2008)

MOTIM: an industrial application using nocs. - Fernando Gehm Moraes; Everton Carara; Daniel V. Pigatto; Ney Laert Vilar Calazans (SBCCI, 2008)

Evaluating the robustness of secure triple track logic through prototyping. - Rafael Soares; Ney Laert Vilar Calazans; Victor Lomné; Philippe Maurine; Lionel Torres; Michel Robert (SBCCI, 2008)

Comparison of network-on-chip mapping algorithms targeting low energy consumption. - César Augusto Missio Marcon; Edson Ifarraguirre Moreno; Ney Laert Vilar Calazans; Fernando Gehm Moraes (IET Comput. Digit. Tech., 2008)

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. - Victor Lomné; Philippe Maurine; Lionel Torres; Michel Robert; Rafael Soares; Ney Calazans (DATE, 2009)

HeMPS - a Framework for NoC-based MPSoC Generation. - Everton Carara; Roberto P. de Oliveira; Ney Laert Vilar Calazans; Fernando Gehm Moraes (ISCAS, 2009)

Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs. - Ewerson Carvalho; César A. M. Marcon; Ney Calazans; Fernando Moraes 001 (SoC, 2009)

A 10 Gbps OTN Framer Implementation Targeting FPGA Devices. - Guilherme Montez Guindani; Frederico Ferlini; Jeferson Oliveira; Ney Laert Vilar Calazans; Daniel V. Pigatto; Fernando Gehm Moraes (ReConFig, 2009)

Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. - Taciano A. Rodolfo; Ney Laert Vilar Calazans; Fernando Gehm Moraes (ReConFig, 2009)

Hermes-A - An Asynchronous NoC Router with Distributed Routing. - Julian J. H. Pontes; Matheus T. Moreira; Fernando Moraes 001; Ney Calazans (PATMOS, 2010)

A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks. - Rafael Soares; Ney Laert Vilar Calazans; Victor Lomné; Amine Dehbaoui; Philippe Maurine; Lionel Torres (SBCCI, 2010)

Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip. - Leonel Tedesco; Thiago R. da Rosa; Fabien Clermidy; Ney Calazans; Fernando Gehm Moraes (SBCCI, 2010)

Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. - Julian J. H. Pontes; Matheus T. Moreira; Fernando Moraes 001; Ney Calazans (SoCC, 2010)

Dynamic Task Mapping for MPSoCs. - Ewerson Luiz de Souza Carvalho; Ney Laert Vilar Calazans; Fernando Gehm Moraes (IEEE Des. Test Comput., 2010)

Adapting a C-element design flow for low power. - Matheus T. Moreira; Bruno Cruz de Oliveira; Julian J. H. Pontes; Fernando Moraes 001; Ney Calazans (ICECS, 2011)

Configurable platform for IC combined tests of total-ionizing dose radiation and electromagnetic immunity. - Juliano Benfica; Letícia Maria Bolzani Poehls; Fabian Vargas 001; José Lipovetzky; Ariel Lutenberg; Sebastián E. García; Edmundo Gatti; Fernando Hernandez; Ney Laert Vilar Calazans (LATW, 2011)

Arbitration and routing impact on NoC design. - Edson I. Moreno; César A. M. Marcon; Ney Laert Vilar Calazans; Fernando Gehm Moraes (International Symposium on Rapid System Prototyping, 2011)

A self-adaptable distributed DFS scheme for NoC-based MPSoCs. - Thiago R. da Rosa; Guilherme Montez Guindani; Douglas de O. Cardoso; Ney Laert Vilar Calazans; Fernando Gehm Moraes (SBCCI, 2011)

A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. - Matheus T. Moreira; Bruno Cruz de Oliveira; Julian J. H. Pontes; Ney Calazans (SoCC, 2011)

A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines. - Rafael Iankowski Soares; Ney Laert Vilar Calazans; Fernando Gehm Moraes; Philippe Maurine; Lionel Torres (IEEE Des. Test Comput., 2011)

CAFES: A framework for intrachip application modeling and communication architecture design. - César A. M. Marcon; Ney Calazans; Edson I. Moreno; Fernando Moraes 001; Fabiano Hessel; Altamiro Amadeu Susin (J. Parallel Distributed Comput., 2011)

Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects. - Julian J. H. Pontes; Ney Calazans; Pascal Vivet (ASYNC, 2012)

An accurate Single Event Effect digital design flow for reliable system level design. - Julian J. H. Pontes; Ney Calazans; Pascal Vivet (DATE, 2012)

A generic FPGA emulation framework. - Fernando Gehm Moraes; Matheus T. Moreira; Carlos Lucas; D. Correa; Douglas de O. Cardoso; Maurício Cecílio Magnaguagno; Guilherme M. Castilhos; Ney Laert Vilar Calazans (ICECS, 2012)

Electrical characterization of a C-Element with LiChEn. - Matheus T. Moreira; Ney Laert Vilar Calazans (ICECS, 2012)

Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits. - Matheus T. Moreira; Ricardo A. Guazzelli; Ney Laert Vilar Calazans (ICECS, 2012)

Impact of C-elements in asynchronous circuits. - Matheus T. Moreira; Bruno Cruz de Oliveira; Fernando Moraes 001; Ney Calazans (ISQED, 2012)

A preliminary study on system-level impact of persistent main memory. - Taciano Perez; Ney Laert Vilar Calazans; César A. F. De Rose (ISQED, 2012)

A spectrum of MPSoC models for design space exploration and its use. - Carlos A. Petry; Eduardo Wächter; Guilherme M. Castilhos; Fernando Gehm Moraes; Ney Laert Vilar Calazans (RSP, 2012)

Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes. - Matheus T. Moreira; Ricardo A. Guazzelli; Ney Laert Vilar Calazans (SBCCI, 2012)

Power consumption reduction in MPSoCs through DFS. - Thiago R. da Rosa; Vivian Larrea; Ney Calazans; Fernando Gehm Moraes (SBCCI, 2012)

Charge sharing aware NCL gates design. - Matheus T. Moreira; Bruno S. Oliveira; Fernando Gehm Moraes; Ney Laert Vilar Calazans (DFTS, 2013)

LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries. - Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans; Luciano Copello Ost (DSD, 2013)

Voltage scaling on C-elements: A speed, power and energy efficiency analysis. - Matheus Trevisan Moreira; Ney Laert Vilar Calazans (ICCD, 2013)

A flexible soft IP core for standard implementations of elliptic curve cryptography in hardware. - Bruno F. Ferreira; Ney Laert Vilar Calazans (ICECS, 2013)

Parity check for m-of-n delay insensitive codes. - Julian J. H. Pontes; Ney Calazans; Pascal Vivet (IOLTS, 2013)

Evaluating the scalability of test buses. - Alexandre M. Amory; Matheus T. Moreira; Ney Laert Vilar Calazans; Fernando Gehm Moraes; Cristiano Lazzari; Marcelo Soares Lubaszewski (ISSoC, 2013)

Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow. - Matheus Trevisan Moreira; Ney Laert Vilar Calazans (ISVLSI, 2013)

Design of NCL gates with the ASCEnD flow. - Matheus T. Moreira; Carlos Henrique Menezes Oliveira; Ricardo C. Porto; Ney Laert Vilar Calazans (LASCAS, 2013)

NCL+: Return-to-one Null Convention Logic. - Matheus T. Moreira; Carlos Henrique Menezes Oliveira; Ricardo C. Porto; Ney Laert Vilar Calazans (MWSCAS, 2013)

BaBaNoC: An asynchronous network-on-chip described in Balsa. - Matheus T. Moreira; Felipe G. Magalhaes; Matheus Gibiluka; Fabiano Hessel; Ney Laert Vilar Calazans (RSP, 2013)

Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy. - Yan Ghidini; Matheus T. Moreira; Lucas Brahm; Thais Webber; Ney Calazans; César A. M. Marcon (SBCCI, 2013)

H2A: A hardened asynchronous network on chip. - Julian J. H. Pontes; Ney Calazans; Pascal Vivet (SBCCI, 2013)

A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design. - Matheus Trevisan Moreira; Michel Evandro Arendt; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans (ASYNC, 2014)

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? - Matheus T. Moreira; Augusto Neutzling; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas; Ney Calazans (ASYNC, 2014)

Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis. - Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck; Ney Laert Vilar Calazans (ACM Great Lakes Symposium on VLSI, 2014)

A design flow for physical synthesis of digital cells with ASTRAN. - Adriel Ziesemer; Ricardo Reis 001; Matheus T. Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans (ACM Great Lakes Symposium on VLSI, 2014)

A monitored NoC with runtime path adaptation. - Edson I. Moreno; Thais Webber; César A. M. Marcon; Fernando Moraes 001; Ney Calazans (ISCAS, 2014)

Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. - Matheus T. Moreira; Julian J. H. Pontes; Ney Laert Vilar Calazans (ISQED, 2014)

Automatic layout synthesis with ASTRAN applied to asynchronous cells. - Adriel Ziesemer; Ricardo Reis 001; Matheus T. Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans (LASCAS, 2014)

Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough? - Ricardo A. Guazzelli; Guilherme Heck; Matheus T. Moreira; Ney Laert Vilar Calazans (LATW, 2014)

Automated Synthesis of Cell Libraries for Asynchronous Circuits. - Matheus Trevisan; Michel Evandro Arendt; Adriel Ziesemer; Ricardo Augusto da Luz Reis; Ney Laert Vilar Calazans (SBCCI, 2014)

Advances on the state of the art in QDI design. - Matheus T. Moreira; Ney Laert Vilar Calazans (VLSI-SoC, 2014)

Spatially Distributed Dual-Spacer Null Convention Logic Design. - Matheus Trevisan Moreira; Guilherme Trojan; Fernando Gehm Moraes; Ney Laert Vilar Calazans (J. Low Power Electron., 2014)

MoNoC: A monitored network on chip with path adaptation mechanism. - Edson I. Moreno; Thais Webber; César A. M. Marcon; Fernando Gehm Moraes; Ney Laert Vilar Calazans (J. Syst. Archit., 2014)

System-level impacts of persistent main memory using a search engine. - Taciano Perez; Ney Laert Vilar Calazans; César A. F. De Rose (Microelectron. J., 2014)

Differentiated Communication Services for NoC-Based MPSoCs. - Everton Alceu Carara; Ney Laert Vilar Calazans; Fernando Gehm Moraes (IEEE Trans. Computers, 2014)

Beware the Dynamic C-Element. - Matheus Trevisan Moreira; Fernando Gehm Moraes; Ney Laert Vilar Calazans (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Performance Optimization and Analysis of Blade Designs under Delay Variability. - Dylan Hand; Hsin-Ho Huang; Benmao Cheng; Yang Zhang 014; Matheus Trevisan Moreira; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2015)

Blade - A Timing Violation Resilient Asynchronous Template. - Dylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang; Danlei Chen; Frederico Butzke; Zhichao Li; Matheus Gibiluka; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2015)

Design and Analysis of Testable Mutual Exclusion Elements. - Yang Zhang 014; Leandro S. Heck; Matheus T. Moreira; David Zar; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2015)

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. - Matheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans (DSD, 2015)

A path towards average-case silicon via asynchronous resilient bundled-data design. - Peter A. Beerel; Ney Laert Vilar Calazans (ECCTD, 2015)

TDTB error detecting latches: Timing violation sensitivity analysis and optimization. - Matheus T. Moreira; Dylan Hand; Peter A. Beerel; Ney Laert Vilar Calazans (ISQED, 2015)

A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies. - Ajay Singhvi; Matheus T. Moreira; Ramy N. Tadros; Ney Laert Vilar Calazans; Peter A. Beerel (ISVLSI, 2015)

BAT-Hermes: A transition-signaling bundled-data NoC router. - Matheus Gibiluka; Matheus Trevisan Moreira; Fernando Gehm Moraes; Ney Laert Vilar Calazans (LASCAS, 2015)

A digitally controlled oscillator for fine-grained local clock generators in MPSoCs. - Guilherme Heck; Leandro S. Heck; Matheus T. Moreira; Fernando Gehm Moraes; Ney Laert Vilar Calazans (LASCAS, 2015)

SDDS-NCL Design: Analysis of Supply Voltage Scaling. - Ricardo A. Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Matheus T. Moreira (SBCCI, 2015)

Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. - Guilherme Heck; Leandro S. Heck; Ajay Singhvi; Matheus T. Moreira; Peter A. Beerel; Ney Laert Vilar Calazans (VLSID, 2015)

Static Differential NCL Gates: Toward Low Power. - Matheus Trevisan Moreira; Michel Evandro Arendt; Fernando Gehm Moraes; Ney Laert Vilar Calazans (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. - Ramy N. Tadros; Weizhe Hua; Matheus Gibiluka; Matheus T. Moreira; Ney Laert Vilar Calazans; Peter A. Beerel (ASYNC, 2016)

ASCEnD-FreePDK45: An open source standard cell library for asynchronous design. - Carlos Henrique Menezes Oliveira; Matheus T. Moreira; Ricardo A. Guazzelli; Ney Laert Vilar Calazans (ICECS, 2016)

The HF-RISC processor: Performance assessment. - Sergio Johann Filho; Matheus T. Moreira; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel (LASCAS, 2016)

Design and analysis of the HF-RISC processor targeting voltage scaling applications. - Felipe Todeschini Bortolon; Sergio Johann Filho; Matheus Gibiluka; Sergio Bampi; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel; Matheus Trevisan Moreira (SBCCI, 2016)

A standard cell characterization flow for non-standard voltage supplies. - Matheus Gibiluka; Matheus Trevisan Moreira; Walter Lau Neto; Ney Laert Vilar Calazans (SBCCI, 2016)

A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits. - Ajay Singhvi; Matheus T. Moreira; Ramy N. Tadros; Ney Laert Vilar Calazans; Peter A. Beerel (ACM J. Emerg. Technol. Comput. Syst., 2016)

A processor for IoT applications: An assessment of design space and trade-offs. - Sergio Johann Filho; Matheus T. Moreira; Leandro S. Heck; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel (Microprocess. Microsystems, 2016)

A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. - Ramy N. Tadros; Weizhe Hua; Matheus T. Moreira; Ney Laert Vilar Calazans; Peter A. Beerel (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Testable MUTEX Design. - Yang Zhang 014; Leandro S. Heck; Matheus T. Moreira; David Zar; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Hardening C-elements against metastability. - Leandro S. Heck; Matheus T. Moreira; Ney Laert Vilar Calazans (ICECS, 2017)

XGT4: An industrial grade, open source tester for multi-gigabit networks. - Leonardo Rezende Juracy; Felipe B. Lazzarotto; Daniel V. Pigatto; Ney Laert Vilar Calazans; Fernando Gehm Moraes (ICECS, 2017)

Go functional model for a RISC-V asynchronous organisation - ARV. - Marcos L. L. Sartori; Ney Laert Vilar Calazans (ICECS, 2017)

A comparison of asynchronous QDI templates using static logic. - Ricardo A. Guazzelli; Matheus T. Moreira; Ney Laert Vilar Calazans (LASCAS, 2017)

Sleep convention logic isochronic fork: an analysis. - Ricardo A. Guazzelli; Matheus T. Moreira; Walter Lau Neto; Ney Laert Vilar Calazans (SBCCI, 2017)

NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization. - Matheus T. Moreira; Peter A. Beerel; Marcos L. L. Sartori; Ney Laert Vilar Calazans (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools. - Marcos L. L. Sartori; Rodrigo N. Wuerdig; Matheus T. Moreira; Ney Laert Vilar Calazans (ASYNC, 2019)

Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations. - Rodrigo N. Wuerdig; Marcos L. L. Sartori; Ney Laert Vilar Calazans (LASCAS, 2019)

An IR-UWB pulse generator using PAM modulation with adaptive PSD in 130nm CMOS process. - Luiz Carlos Moreira; José Fontebasso Neto; Walter Silva Oliveira; Thiago Ferauche; Guilherme Heck; Ney Laert Vilar Calazans; Fernando Gehm Moraes (SBCCI, 2019)

A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow. - Marcos L. L. Sartori; Matheus T. Moreira; Ney Laert Vilar Calazans (ASYNC, 2020)

Leveraging QDI Robustness to Simplify the Design of IoT Circuits. - Marcos L. L. Sartori; Rodrigo N. Wuerdig; Matheus T. Moreira; Sergio Bampi; Ney Laert Vilar Calazans (ISCAS, 2020)

Towards an Integrated Software Development Environment for Robotic Applications in MPSoCs with Support for Energy Estimations. - Paulo H. Vancin; Anderson R. P. Domingues; Marcelo Paravisi; Sergio F. Johann; Ney Laert Vilar Calazans; Alexandre M. Amory (ISCAS, 2020)

Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. - Taciano A. Rodolfo; Marcos L. L. Sartori; Matheus T. Moreira; Ney Laert Vilar Calazans (ISCAS, 2021)

Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers. - Rodrigo N. Wuerdig; Marcos L. L. Sartori; Brunno A. Abreu; Sergio Bampi; Ney Laert Vilar Calazans (ISCAS, 2022)

Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design. - Marcos Luiggi Lemos Sartori; Willian Analdo Nunes; Ney Laert Vilar Calazans (SBCCI, 2022)

Assessment of Communication Protocols' Latency in Co-processing Robotic Systems. - Eduardo Pereira; Lucas Luza; Nicolas Moura; Luciano Ost; Ney Calazans; Fernando Gehm Moraes; Rafael Garibotti (NEWCAS, 2023)

Assessment of Lightweight Cryptography Algorithms on ARM Cortex-M Processors. - Nicolas Moura; Joaquim Lucena; Eduardo Pereira; Ney Calazans; Luciano Ost; Fernando Moraes 001; Rafael Garibotti (SBCCI, 2023)

Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V. - Willian Analdo Nunes; Marcos Luiggi Lemos Sartori; Matheus Trevisan Moreira; Fernando Gehm Moraes; Ney Laert Vilar Calazans (SBCCI, 2023)

Soft Error Assessment of UAV Control Algorithms Running in Resource-Constrained Microprocessors. - Alex Hanneman; Jonas Gava; Paulo Vancin; Aqsa Kk Kaim-Khani; Sam Amiri; Rafael Garibotti; Fernando Moraes 001; Ney Calazans; Ricardo Reis 001; Luciano Ost (ISVLSI, 2024)

Hardware Acceleration of Authenticated Encryption with Associated Data via RISC-V Instruction Set Extensions in Low Power Embedded Systems. - Carlos Gabriel de Araujo Gewehr; Nicolas Moura; Lucas Luza; Eduardo Bernardon; Ney Calazans; Rafael Garibotti; Fernando Gehm Moraes (LASCAS, 2024)

Exploring Soft Error Susceptibility in FET Devices via Geant4 Simulation. - Elisa Garcia Pereira; Rafael Garibotti; Ney Calazans; Luciano Ost; Fernando Moraes 001 (LASCAS, 2025)

Guest Editors' Introduction: SBCCI 2023. - Ney Calazans; Bruno Zatt (IEEE Des. Test, 2025)