A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability. - Dirk Reese; Eric Chun; Sammy Cheung; Edmond Lau; Michael Chu; Gwen Liang; Nghia Van Tran; Brad Vest; Richard Smolen; Minchang Liang; Seshan Sekariapuram; Behzad Nouban; et al. (CICC, 1998)