Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA. - Nguyen My Qui; Chang Hong Lin; Poki Chen (IEEE Access, 2020)

High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters. - Poki Chen; Jian-Ting Lan; Ruei-Ting Wang; Nguyen My Qui; John Carl Joel Salao Marquez; Seiji Kajihara; Yousuke Miyake (IEEE Trans. Very Large Scale Integr. Syst., 2020)