A Design for Machines with Built-In Tolerance to Soft Errors. - Yvon Savaria; Vinod K. Agarwal; Nicholas C. Rumin; Jeremiah F. Hayes (ITC, 1984)

The McBOOLE logic minimizer. - Michel R. Dagenais; Vinod K. Agarwal; Nicholas C. Rumin (DAC, 1985)

A Theory for the Design of Soft-Error-Tolerant VLSI Circuits. - Yvon Savaria; Jeremiah F. Hayes; Nicholas C. Rumin; Vinod K. Agarwal (IEEE J. Sel. Areas Commun., 1986)

Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits. - Yvon Savaria; Nicholas C. Rumin; Jeremiah F. Hayes; Vinold K. Agarwal (Proc. IEEE, 1986)

McBOOLE: A New Procedure for Exact Logic Minimization. - Michel R. Dagenais; Vinod K. Agarwal; Nicholas C. Rumin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

Delay computation in switch-level models of non-treelike MOS circuits. - Denis Martin; Nicholas C. Rumin (ICCAD, 1988)

Worst-case Delay Estimation of Transistor Groups. - Serge Gaiotti; Michel R. Dagenais; Nicholas C. Rumin (DAC, 1989)

Magnitude classes in switch-level modeling. - Eduard Cerny; John P. Hayes; Nicholas C. Rumin (ICCD, 1989)

On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches. - Michel R. Dagenais; Nicholas C. Rumin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

A recursive technique for computing delays in series-parallel MOS transistor circuits. - Jean Paul Caisso; Eduard Cerny; Nicholas C. Rumin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

A fault-tolerant array processor designed for testability and self-reconfiguration. - Ajai Jain; Babu Mandava; Janusz Rajski; Nicholas C. Rumin (IEEE J. Solid State Circuits, 1991)

Delay and bus current evaluation in CMOS logic circuits. - Abdolreza Nabavi-Lishi; Nicholas C. Rumin (ICCAD, 1992)

Accuracy of magnitude-class calculations in switch-level modeling. - Eduard Cerny; John P. Hayes; Nicholas C. Rumin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Transistor-level estimation of worst-case delays in MOS VLSI circuits. - Michel R. Dagenais; Serge Gaiotti; Nicholas C. Rumin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Delay prediction from resistance-capacitance models of general MOS circuits. - Denis Martin; Nicholas C. Rumin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Inverter-based Models for Current Analysis of CMOS Logic Circuits. - Abdolreza Nabavi-Lishi; Nicholas C. Rumin (ISCAS, 1994)

Inverter models of CMOS gates for supply current and delay evaluation. - Abdolreza Nabavi-Lishi; Nicholas C. Rumin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Bounding Switching Activity in CMOS Circuits Using Constraint Resolution. - Jindrich Zejda; Eduard Cerny; S. Shenoy; Nicholas C. Rumin (ED&TC, 1996)

An analytical current, delay, and power model for the submicron CMOS inverter. - Anas A. Hamoui; Nicholas C. Rumin (ICECS, 1999)

Delay and current estimation in a CMOS inverter with an RC load. - Mohamed Hafed; Mourad Oulmane; Nicholas C. Rumin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Explicit delay metric for interconnect optimization. - Min Ma; Mourad Oulmane; Nicholas C. Rumin (ISCAS (3), 2005)