Segmentation and preliminary recognition of madrigals notated in white mensural notation. - Nicholas P. Carter (Mach. Vis. Appl., 1992)

Hardware Support for Fast Capability-based Addressing. - Nicholas P. Carter; Stephen W. Keckler; William J. Dally (ASPLOS, 1994)

Conversion of the Haydn symphonies into electronic form using automatic score recognition: a pilot study. - Nicholas P. Carter (Document Recognition, 1994)

The M-machine multicomputer. - Marco Fillo; Stephen W. Keckler; William J. Dally; Nicholas P. Carter; Andrew Chang 001; Yevgeny Gurevich; Whay Sing Lee (Int. J. Parallel Program., 1997)

The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline. - Andrew Chang 001; William J. Dally; Stephen W. Keckler; Nicholas P. Carter; Whay Sing Lee (ICCD, 1998)

Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor. - Stephen W. Keckler; William J. Dally; Daniel Maskit; Nicholas P. Carter; Andrew Chang 001; Whay Sing Lee (ISCA, 1998)

An Efficient, Protected Message Interface. - Whay Sing Lee; William J. Dally; Stephen W. Keckler; Nicholas P. Carter; Andrew Chang 001 (Computer, 1998)

Processor mechanisms for software shared memory. - Nicholas P. Carter (1999)

Processor Mechanisms for Software Shared Memory. - Nicholas P. Carter; William J. Dally; Whay Sing Lee; Stephen W. Keckler; Andrew Chang 001 (ISHPC, 2000)

Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor. - Jeffrey J. Cook; Derek B. Gottlieb; Joshua D. Walstrom; Steve Ferrera; Chi-Wei Wang; Nicholas P. Carter (FCCM, 2002)

The Design of the Amalgam Reconfigurable Cluster. - Joshua D. Walstrom; Jeffrey J. Cook; Derek B. Gottlieb; Steve Ferrera; Chi-Wei Wang; Nicholas P. Carter (FCCM, 2002)

Clustered programmable-reconfigurable processors. - Derek B. Gottlieb; Jeffrey J. Cook; Joshua D. Walstrom; Steve Ferrera; Chi-Wei Wang; Nicholas P. Carter (FPT, 2002)

Reconfigurable Circuits Using Hybrid Hall Effect Devices. - Steve Ferrera; Nicholas P. Carter (FPL, 2003)

Mapping computation kernels to clustered programmable-reconfigurable processors. - Jeffrey J. Cook; Lee Baugh; Derek B. Gottlieb; Nicholas P. Carter (FPT, 2003)

Microprocessor Interfacing Laboratory. - Derek B. Gottlieb; Nicholas P. Carter (MSE, 2003)

A magnetoelectronic macrocell employing reconfigurable threshold logic. - Steve Ferrera; Nicholas P. Carter (FPGA, 2004)

A reconfigurable unit for a clustered programmable-reconfigurable processor. - Richard B. Kujoth; Chi-Wei Wang; Derek B. Gottlieb; Jeffrey J. Cook; Nicholas P. Carter (FPGA, 2004)

Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction. - Jeffrey M. Stine; Nicholas P. Carter; José Flich (IEEE Comput. Archit. Lett., 2004)

Reconfigurable magnetoelectronic circuits for threshold logic. - Nicholas P. Carter; Steve Ferrera (Int. J. Circuit Theory Appl., 2004)

Hall-effect circuits and architectures for non-volatile system design. - Nicholas P. Carter; Steve Ferrera; Love Kothari; Stanley Ye (ECCTD, 2005)

Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor. - Chi-Wei Wang; Nicholas P. Carter; Richard B. Kujoth; Jeffrey J. Cook; Derek B. Gottlieb (FPL, 2005)

Gated hybrid Hall effect device on silicon. - Pratyush Das Kanungo; Alexandra Imre; Bin Wu; Alexei O. Orlov; Gregory L. Snider; Wolfgang Porod; Nicholas P. Carter (Microelectron. J., 2005)

Modeling wire delay, area, power, and performance in a simulation infrastructure. - Nicholas P. Carter; Azmat Hussain (IBM J. Res. Dev., 2006)

A magnetoelectronic register file cell for a self-checkpointing microprocessor. - Nitin Navale; Erica Lundgren; Nicholas P. Carter (Int. J. Circuit Theory Appl., 2007)

A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor. - Richard B. Kujoth; Chi-Wei Wang; Jeffrey J. Cook; Derek B. Gottlieb; Nicholas P. Carter (Microprocess. Microsystems, 2007)

Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices. - Love Kothari; Nicholas P. Carter (IEEE Trans. Computers, 2007)

Design techniques for cross-layer resilience. - Nicholas P. Carter; Helia Naeimi; Donald S. Gardner (DATE, 2010)

Vision for cross-layer optimization to address the dual challenges of energy and reliability. - André DeHon; Heather M. Quinn; Nicholas P. Carter (DATE, 2010)

DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism. - Byn Choi; Rakesh Komuravelli; Hyojin Sung; Robert Smolinski; Nima Honarmand; Sarita V. Adve; Vikram S. Adve; Nicholas P. Carter; Ching-Tsun Chou (PACT, 2011)

Runnemede: An architecture for Ubiquitous High-Performance Computing. - Nicholas P. Carter; Aditya Agrawal; Shekhar Borkar; Romain Cledat; Howard David; Dave Dunning; Joshua B. Fryman; Ivan Ganev; Roger A. Golliver; Rob C. Knauerhase; Richard Lethin; Benoît Meister; et al. (HPCA, 2013)